From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9058 invoked by alias); 8 Dec 2003 06:10:19 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 9040 invoked from network); 8 Dec 2003 06:10:11 -0000 Received: from unknown (HELO mail04.idc.renesas.com) (202.234.163.13) by sources.redhat.com with SMTP; 8 Dec 2003 06:10:11 -0000 Received: (from root@localhost) by guardian01.idc.renesas.com with id hB869whv004663; Mon, 8 Dec 2003 15:09:58 +0900 (JST) Received: from unknown [172.20.8.68] by guardian01.idc.renesas.com with SMTP id RAA04662 ; Mon, 8 Dec 2003 15:09:58 +0900 Received: from dnma02 (dnma02.rso.renesas.com [10.15.11.200]) by dnma01.rso.renesas.com (iPlanet Messaging Server 5.2 HotFix 1.12 (built Feb 13 2003)) with ESMTP id <0HPK004BMBSHUW@dnma01.rso.renesas.com>; Mon, 08 Dec 2003 15:09:53 +0900 (JST) Received: from t1pcapricot.tool.maec.co.jp ([10.145.105.37]) by dnma02.rso.renesas.com (iPlanet Messaging Server 5.2 HotFix 1.12 (built Feb 13 2003)) with SMTP id <0HPK000I0BSBB8@dnma02.rso.renesas.com>; Mon, 08 Dec 2003 15:09:49 +0900 (JST) Date: Mon, 08 Dec 2003 06:10:00 -0000 From: Kazuhiro Inaoka Subject: Re: [PATCH] Add new model m32r2 of Renesas M32R. To: Andrew Cagney Cc: gdb-patches@sources.redhat.com Message-id: <00cd01c3bd52$a0e47300$2569910a@tool.maec.co.jp> MIME-version: 1.0 X-MIMEOLE: Produced By Microsoft MimeOLE V5.50.4807.1700 Content-type: multipart/mixed; boundary="Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ)" X-Priority: 3 X-MSMail-priority: Normal References: <003901c3b8c4$b3599840$2569910a@tool.maec.co.jp> <3FD2960C.1000100@gnu.org> X-SW-Source: 2003-12/txt/msg00251.txt.bz2 This is a multi-part message in MIME format. --Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ) Content-type: text/plain; charset=iso-2022-jp Content-transfer-encoding: 7BIT Content-length: 1220 Hello Andrew > - did I miss the file model2.c? I can generate model2.c with cgen in current-cvs. > - does it build for you? For --target=m32r-elf I see: I send to my m32r2 target's files to build with --target=m32r-elf --enable-cgen-maint. Kazuhiro > > ChangeLog/sim/m32r > > > > 2003-12-02 Kazuhiro Inaoka > > > > * Makefile.in : Add new machine m32r2. > > * m32r2.c : New file for m32r2. > > * mloop2.in : Ditto > > * model2.c : Ditto > > * sem2-switch.c : Ditto > > * m32r-sim.h : Add EVB register. > > * sim-if.h : Ditto > > * sim-main.h : Ditto > > * traps.c : Ditto > > Two questions? > > - did I miss the file model2.c? > - does it build for you? For --target=m32r-elf I see: > > /home/scratch/GDB/src/sim/m32r/sim-main.h:64: parse error before > `M32R2F_CPU_DATA' > /home/scratch/GDB/src/sim/m32r/sim-main.h:64: warning: no semicolon at > end of struct or union > In file included from /home/scratch/GDB/src/sim/m32r/m32r2.c:25: > /home/scratch/GDB/src/sim/m32r/../common/cgen-mem.h: In function `GETMEMQI': > /home/scratch/GDB/src/sim/m32r/../common/cgen-mem.h:50: dereferencing > pointer to incomplete type > > Andrew > > --Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ) Content-type: application/octet-stream; name=cpuall.h Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=cpuall.h Content-length: 2332 /* Simulator CPU header for m32r.=0A= =0A= THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= =0A= Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foun= dation, Inc.=0A= =0A= This file is part of the GNU simulators.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= */=0A= =0A= #ifndef M32R_CPUALL_H=0A= #define M32R_CPUALL_H=0A= =0A= /* Include files for each cpu family. */=0A= =0A= #ifdef WANT_CPU_M32RBF=0A= #include "eng.h"=0A= #include "cgen-engine.h"=0A= #include "cpu.h"=0A= #include "decode.h"=0A= #endif=0A= =0A= #ifdef WANT_CPU_M32RXF=0A= #include "engx.h"=0A= #include "cgen-engine.h"=0A= #include "cpux.h"=0A= #include "decodex.h"=0A= #endif=0A= =0A= #ifdef WANT_CPU_M32R2F=0A= #include "eng2.h"=0A= #include "cgen-engine.h"=0A= #include "cpu2.h"=0A= #include "decode2.h"=0A= #endif=0A= =0A= extern const MACH m32r_mach;=0A= extern const MACH m32rx_mach;=0A= extern const MACH m32r2_mach;=0A= =0A= #ifndef WANT_CPU=0A= /* The ARGBUF struct. */=0A= struct argbuf {=0A= /* These are the baseclass definitions. */=0A= IADDR addr;=0A= const IDESC *idesc;=0A= char trace_p;=0A= char profile_p;=0A= /* ??? Temporary hack for skip insns. */=0A= char skip_count;=0A= char unused;=0A= /* cpu specific data follows */=0A= };=0A= #endif=0A= =0A= #ifndef WANT_CPU=0A= /* A cached insn.=0A= =0A= ??? SCACHE used to contain more than just argbuf. We could delete the= =0A= type entirely and always just use ARGBUF, but for future concerns and as= =0A= a level of abstraction it is left in. */=0A= =0A= struct scache {=0A= struct argbuf argbuf;=0A= };=0A= #endif=0A= =0A= #endif /* M32R_CPUALL_H */=0A= --Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ) Content-type: application/octet-stream; name=model2.c Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=model2.c Content-length: 112994 /* Simulator model support for m32r2f.=0A= =0A= THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= =0A= Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foun= dation, Inc.=0A= =0A= This file is part of the GNU simulators.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= */=0A= =0A= #define WANT_CPU m32r2f=0A= #define WANT_CPU_M32R2F=0A= =0A= #include "sim-main.h"=0A= =0A= /* The profiling data is recorded here, but is accessed via the profiling= =0A= mechanism. After all, this is information for profiling. */=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= =0A= /* Model handlers for each insn. */=0A= =0A= static int=0A= model_m32r2_add (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_add3 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_and (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_and3 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_and3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_or (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_or3 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_and3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_xor (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_xor3 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_and3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_addi (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_addv (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_addv3 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_addx (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bc8 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bc24 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_beq (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 3)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_beqz (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bgez (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bgtz (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_blez (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bltz (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bnez (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bl8 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bl24 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bcl8 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 4)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bcl24 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 4)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bnc8 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bnc24 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bne (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 3)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 1, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bra8 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bra24 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bncl8 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 4)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bncl24 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= if (insn_referenced & (1 << 4)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_cmp (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_cmpi (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_cmpu (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_cmpui (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_cmpeq (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_cmpz (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_div (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_divu (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_rem (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_remu (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_remh (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_remuh (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_remb (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_remub (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_divuh (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_divb (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_divub (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_divh (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 0)) referenced |=3D 1 << 1;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_jc (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= if (insn_referenced & (1 << 1)) referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_jnc (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= if (insn_referenced & (1 << 1)) referenced |=3D 1 << 0;=0A= if (insn_referenced & (1 << 2)) referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_jl (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_jmp (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cti (current_cpu, idesc, 0, referenced= , in_sr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ld (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ld_d (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ldb (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ldb_d (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ldh (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ldh_d (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ldub (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ldub_d (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_lduh (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_lduh_d (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ld_plus (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_sr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ld24 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld24.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ldi8 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_ldi16 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_lock (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_machi_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_maclo_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mul (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mullo_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mv (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mvfc (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_src1);=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_src1);=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mvtc (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= referenced |=3D 1 << 0;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_neg (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_nop (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_not (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_rte (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_seth (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_seth.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sll (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sll3 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_slli (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sra (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sra3 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_srai (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_srl (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_srl3 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_srli (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_st (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_st_d (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_stb (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_stb_d (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sth (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sth_d (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_st_plus (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_src2);=0A= out_dr =3D FLD (out_src2);=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sth_plus (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_src2);=0A= out_dr =3D FLD (out_src2);=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_stb_plus (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_src2);=0A= out_dr =3D FLD (out_src2);=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_st_minus (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D 0;=0A= INT in_src2 =3D 0;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_store (current_cpu, idesc, 0, referenc= ed, in_src1, in_src2);=0A= }=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_dr =3D FLD (in_src2);=0A= out_dr =3D FLD (out_src2);=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 1, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sub (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_subv (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_subx (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= in_dr =3D FLD (in_dr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_trap (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_trap.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_unlock (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D 0;=0A= INT out_dr =3D 0;=0A= cycles +=3D m32r2f_model_m32r2_u_load (current_cpu, idesc, 0, reference= d, in_sr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_satb (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sath (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sat (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= out_dr =3D FLD (out_dr);=0A= if (insn_referenced & (1 << 1)) referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 2;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_cmp (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sadd (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_macwu1 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_msblo (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_maclh1 (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_src1 =3D -1;=0A= INT in_src2 =3D -1;=0A= in_src1 =3D FLD (in_src1);=0A= in_src2 =3D FLD (in_src2);=0A= referenced |=3D 1 << 0;=0A= referenced |=3D 1 << 1;=0A= cycles +=3D m32r2f_model_m32r2_u_mac (current_cpu, idesc, 0, referenced= , in_src1, in_src2);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_sc (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_snc (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_clrpsw (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_setpsw (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bset (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= referenced |=3D 1 << 0;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_bclr (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= referenced |=3D 1 << 0;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= static int=0A= model_m32r2_btst (SIM_CPU *current_cpu, void *sem_arg)=0A= {=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= const ARGBUF * UNUSED abuf =3D SEM_ARGBUF ((SEM_ARG) sem_arg);=0A= const IDESC * UNUSED idesc =3D abuf->idesc;=0A= int cycles =3D 0;=0A= {=0A= int referenced =3D 0;=0A= int UNUSED insn_referenced =3D abuf->written;=0A= INT in_sr =3D -1;=0A= INT in_dr =3D -1;=0A= INT out_dr =3D -1;=0A= in_sr =3D FLD (in_sr);=0A= referenced |=3D 1 << 0;=0A= cycles +=3D m32r2f_model_m32r2_u_exec (current_cpu, idesc, 0, reference= d, in_sr, in_dr, out_dr);=0A= }=0A= return cycles;=0A= #undef FLD=0A= }=0A= =0A= /* We assume UNIT_NONE =3D=3D 0 because the tables don't always terminate= =0A= entries with it. */=0A= =0A= /* Model timing data for `m32r2'. */=0A= =0A= static const INSN_TIMING m32r2_timing[] =3D {=0A= { M32R2F_INSN_X_INVALID, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },=0A= { M32R2F_INSN_X_AFTER, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },=0A= { M32R2F_INSN_X_BEFORE, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },=0A= { M32R2F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },=0A= { M32R2F_INSN_X_CHAIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },=0A= { M32R2F_INSN_X_BEGIN, 0, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } },=0A= { M32R2F_INSN_ADD, model_m32r2_add, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_ADD3, model_m32r2_add3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_AND, model_m32r2_and, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_AND3, model_m32r2_and3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_OR, model_m32r2_or, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }= ,=0A= { M32R2F_INSN_OR3, model_m32r2_or3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_XOR, model_m32r2_xor, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_XOR3, model_m32r2_xor3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_ADDI, model_m32r2_addi, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_ADDV, model_m32r2_addv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_ADDV3, model_m32r2_addv3, { { (int) UNIT_M32R2_U_EXEC, 1, 1= } } },=0A= { M32R2F_INSN_ADDX, model_m32r2_addx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_BC8, model_m32r2_bc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } = },=0A= { M32R2F_INSN_BC24, model_m32r2_bc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } = } },=0A= { M32R2F_INSN_BEQ, model_m32r2_beq, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, {= (int) UNIT_M32R2_U_CMP, 1, 0 } } },=0A= { M32R2F_INSN_BEQZ, model_m32r2_beqz, { { (int) UNIT_M32R2_U_CTI, 1, 1 },= { (int) UNIT_M32R2_U_CMP, 1, 0 } } },=0A= { M32R2F_INSN_BGEZ, model_m32r2_bgez, { { (int) UNIT_M32R2_U_CTI, 1, 1 },= { (int) UNIT_M32R2_U_CMP, 1, 0 } } },=0A= { M32R2F_INSN_BGTZ, model_m32r2_bgtz, { { (int) UNIT_M32R2_U_CTI, 1, 1 },= { (int) UNIT_M32R2_U_CMP, 1, 0 } } },=0A= { M32R2F_INSN_BLEZ, model_m32r2_blez, { { (int) UNIT_M32R2_U_CTI, 1, 1 },= { (int) UNIT_M32R2_U_CMP, 1, 0 } } },=0A= { M32R2F_INSN_BLTZ, model_m32r2_bltz, { { (int) UNIT_M32R2_U_CTI, 1, 1 },= { (int) UNIT_M32R2_U_CMP, 1, 0 } } },=0A= { M32R2F_INSN_BNEZ, model_m32r2_bnez, { { (int) UNIT_M32R2_U_CTI, 1, 1 },= { (int) UNIT_M32R2_U_CMP, 1, 0 } } },=0A= { M32R2F_INSN_BL8, model_m32r2_bl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } = },=0A= { M32R2F_INSN_BL24, model_m32r2_bl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 } = } },=0A= { M32R2F_INSN_BCL8, model_m32r2_bcl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } = } },=0A= { M32R2F_INSN_BCL24, model_m32r2_bcl24, { { (int) UNIT_M32R2_U_CTI, 1, 1 = } } },=0A= { M32R2F_INSN_BNC8, model_m32r2_bnc8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } = } },=0A= { M32R2F_INSN_BNC24, model_m32r2_bnc24, { { (int) UNIT_M32R2_U_CTI, 1, 1 = } } },=0A= { M32R2F_INSN_BNE, model_m32r2_bne, { { (int) UNIT_M32R2_U_CTI, 1, 1 }, {= (int) UNIT_M32R2_U_CMP, 1, 0 } } },=0A= { M32R2F_INSN_BRA8, model_m32r2_bra8, { { (int) UNIT_M32R2_U_CTI, 1, 1 } = } },=0A= { M32R2F_INSN_BRA24, model_m32r2_bra24, { { (int) UNIT_M32R2_U_CTI, 1, 1 = } } },=0A= { M32R2F_INSN_BNCL8, model_m32r2_bncl8, { { (int) UNIT_M32R2_U_CTI, 1, 1 = } } },=0A= { M32R2F_INSN_BNCL24, model_m32r2_bncl24, { { (int) UNIT_M32R2_U_CTI, 1, = 1 } } },=0A= { M32R2F_INSN_CMP, model_m32r2_cmp, { { (int) UNIT_M32R2_U_CMP, 1, 1 } } = },=0A= { M32R2F_INSN_CMPI, model_m32r2_cmpi, { { (int) UNIT_M32R2_U_CMP, 1, 1 } = } },=0A= { M32R2F_INSN_CMPU, model_m32r2_cmpu, { { (int) UNIT_M32R2_U_CMP, 1, 1 } = } },=0A= { M32R2F_INSN_CMPUI, model_m32r2_cmpui, { { (int) UNIT_M32R2_U_CMP, 1, 1 = } } },=0A= { M32R2F_INSN_CMPEQ, model_m32r2_cmpeq, { { (int) UNIT_M32R2_U_CMP, 1, 1 = } } },=0A= { M32R2F_INSN_CMPZ, model_m32r2_cmpz, { { (int) UNIT_M32R2_U_CMP, 1, 1 } = } },=0A= { M32R2F_INSN_DIV, model_m32r2_div, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } = } },=0A= { M32R2F_INSN_DIVU, model_m32r2_divu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 = } } },=0A= { M32R2F_INSN_REM, model_m32r2_rem, { { (int) UNIT_M32R2_U_EXEC, 1, 37 } = } },=0A= { M32R2F_INSN_REMU, model_m32r2_remu, { { (int) UNIT_M32R2_U_EXEC, 1, 37 = } } },=0A= { M32R2F_INSN_REMH, model_m32r2_remh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 = } } },=0A= { M32R2F_INSN_REMUH, model_m32r2_remuh, { { (int) UNIT_M32R2_U_EXEC, 1, 2= 1 } } },=0A= { M32R2F_INSN_REMB, model_m32r2_remb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 = } } },=0A= { M32R2F_INSN_REMUB, model_m32r2_remub, { { (int) UNIT_M32R2_U_EXEC, 1, 2= 1 } } },=0A= { M32R2F_INSN_DIVUH, model_m32r2_divuh, { { (int) UNIT_M32R2_U_EXEC, 1, 2= 1 } } },=0A= { M32R2F_INSN_DIVB, model_m32r2_divb, { { (int) UNIT_M32R2_U_EXEC, 1, 21 = } } },=0A= { M32R2F_INSN_DIVUB, model_m32r2_divub, { { (int) UNIT_M32R2_U_EXEC, 1, 2= 1 } } },=0A= { M32R2F_INSN_DIVH, model_m32r2_divh, { { (int) UNIT_M32R2_U_EXEC, 1, 21 = } } },=0A= { M32R2F_INSN_JC, model_m32r2_jc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },= =0A= { M32R2F_INSN_JNC, model_m32r2_jnc, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } = },=0A= { M32R2F_INSN_JL, model_m32r2_jl, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } },= =0A= { M32R2F_INSN_JMP, model_m32r2_jmp, { { (int) UNIT_M32R2_U_CTI, 1, 1 } } = },=0A= { M32R2F_INSN_LD, model_m32r2_ld, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } } }= ,=0A= { M32R2F_INSN_LD_D, model_m32r2_ld_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2 }= } },=0A= { M32R2F_INSN_LDB, model_m32r2_ldb, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } }= },=0A= { M32R2F_INSN_LDB_D, model_m32r2_ldb_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2= } } },=0A= { M32R2F_INSN_LDH, model_m32r2_ldh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 } }= },=0A= { M32R2F_INSN_LDH_D, model_m32r2_ldh_d, { { (int) UNIT_M32R2_U_LOAD, 1, 2= } } },=0A= { M32R2F_INSN_LDUB, model_m32r2_ldub, { { (int) UNIT_M32R2_U_LOAD, 1, 1 }= } },=0A= { M32R2F_INSN_LDUB_D, model_m32r2_ldub_d, { { (int) UNIT_M32R2_U_LOAD, 1,= 2 } } },=0A= { M32R2F_INSN_LDUH, model_m32r2_lduh, { { (int) UNIT_M32R2_U_LOAD, 1, 1 }= } },=0A= { M32R2F_INSN_LDUH_D, model_m32r2_lduh_d, { { (int) UNIT_M32R2_U_LOAD, 1,= 2 } } },=0A= { M32R2F_INSN_LD_PLUS, model_m32r2_ld_plus, { { (int) UNIT_M32R2_U_LOAD, = 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },=0A= { M32R2F_INSN_LD24, model_m32r2_ld24, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_LDI8, model_m32r2_ldi8, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_LDI16, model_m32r2_ldi16, { { (int) UNIT_M32R2_U_EXEC, 1, 1= } } },=0A= { M32R2F_INSN_LOCK, model_m32r2_lock, { { (int) UNIT_M32R2_U_LOAD, 1, 1 }= } },=0A= { M32R2F_INSN_MACHI_A, model_m32r2_machi_a, { { (int) UNIT_M32R2_U_MAC, 1= , 1 } } },=0A= { M32R2F_INSN_MACLO_A, model_m32r2_maclo_a, { { (int) UNIT_M32R2_U_MAC, 1= , 1 } } },=0A= { M32R2F_INSN_MACWHI_A, model_m32r2_macwhi_a, { { (int) UNIT_M32R2_U_MAC,= 1, 1 } } },=0A= { M32R2F_INSN_MACWLO_A, model_m32r2_macwlo_a, { { (int) UNIT_M32R2_U_MAC,= 1, 1 } } },=0A= { M32R2F_INSN_MUL, model_m32r2_mul, { { (int) UNIT_M32R2_U_EXEC, 1, 4 } }= },=0A= { M32R2F_INSN_MULHI_A, model_m32r2_mulhi_a, { { (int) UNIT_M32R2_U_MAC, 1= , 1 } } },=0A= { M32R2F_INSN_MULLO_A, model_m32r2_mullo_a, { { (int) UNIT_M32R2_U_MAC, 1= , 1 } } },=0A= { M32R2F_INSN_MULWHI_A, model_m32r2_mulwhi_a, { { (int) UNIT_M32R2_U_MAC,= 1, 1 } } },=0A= { M32R2F_INSN_MULWLO_A, model_m32r2_mulwlo_a, { { (int) UNIT_M32R2_U_MAC,= 1, 1 } } },=0A= { M32R2F_INSN_MV, model_m32r2_mv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }= ,=0A= { M32R2F_INSN_MVFACHI_A, model_m32r2_mvfachi_a, { { (int) UNIT_M32R2_U_EX= EC, 1, 2 } } },=0A= { M32R2F_INSN_MVFACLO_A, model_m32r2_mvfaclo_a, { { (int) UNIT_M32R2_U_EX= EC, 1, 2 } } },=0A= { M32R2F_INSN_MVFACMI_A, model_m32r2_mvfacmi_a, { { (int) UNIT_M32R2_U_EX= EC, 1, 2 } } },=0A= { M32R2F_INSN_MVFC, model_m32r2_mvfc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_MVTACHI_A, model_m32r2_mvtachi_a, { { (int) UNIT_M32R2_U_EX= EC, 1, 1 } } },=0A= { M32R2F_INSN_MVTACLO_A, model_m32r2_mvtaclo_a, { { (int) UNIT_M32R2_U_EX= EC, 1, 1 } } },=0A= { M32R2F_INSN_MVTC, model_m32r2_mvtc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_NEG, model_m32r2_neg, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_NOP, model_m32r2_nop, { { (int) UNIT_M32R2_U_EXEC, 1, 0 } }= },=0A= { M32R2F_INSN_NOT, model_m32r2_not, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_RAC_DSI, model_m32r2_rac_dsi, { { (int) UNIT_M32R2_U_MAC, 1= , 1 } } },=0A= { M32R2F_INSN_RACH_DSI, model_m32r2_rach_dsi, { { (int) UNIT_M32R2_U_MAC,= 1, 1 } } },=0A= { M32R2F_INSN_RTE, model_m32r2_rte, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_SETH, model_m32r2_seth, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SLL, model_m32r2_sll, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_SLL3, model_m32r2_sll3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SLLI, model_m32r2_slli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SRA, model_m32r2_sra, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_SRA3, model_m32r2_sra3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SRAI, model_m32r2_srai, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SRL, model_m32r2_srl, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_SRL3, model_m32r2_srl3, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SRLI, model_m32r2_srli, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_ST, model_m32r2_st, { { (int) UNIT_M32R2_U_STORE, 1, 1 } } = },=0A= { M32R2F_INSN_ST_D, model_m32r2_st_d, { { (int) UNIT_M32R2_U_STORE, 1, 2 = } } },=0A= { M32R2F_INSN_STB, model_m32r2_stb, { { (int) UNIT_M32R2_U_STORE, 1, 1 } = } },=0A= { M32R2F_INSN_STB_D, model_m32r2_stb_d, { { (int) UNIT_M32R2_U_STORE, 1, = 2 } } },=0A= { M32R2F_INSN_STH, model_m32r2_sth, { { (int) UNIT_M32R2_U_STORE, 1, 1 } = } },=0A= { M32R2F_INSN_STH_D, model_m32r2_sth_d, { { (int) UNIT_M32R2_U_STORE, 1, = 2 } } },=0A= { M32R2F_INSN_ST_PLUS, model_m32r2_st_plus, { { (int) UNIT_M32R2_U_STORE,= 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },=0A= { M32R2F_INSN_STH_PLUS, model_m32r2_sth_plus, { { (int) UNIT_M32R2_U_STOR= E, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },=0A= { M32R2F_INSN_STB_PLUS, model_m32r2_stb_plus, { { (int) UNIT_M32R2_U_STOR= E, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },=0A= { M32R2F_INSN_ST_MINUS, model_m32r2_st_minus, { { (int) UNIT_M32R2_U_STOR= E, 1, 1 }, { (int) UNIT_M32R2_U_EXEC, 1, 0 } } },=0A= { M32R2F_INSN_SUB, model_m32r2_sub, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_SUBV, model_m32r2_subv, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SUBX, model_m32r2_subx, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_TRAP, model_m32r2_trap, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_UNLOCK, model_m32r2_unlock, { { (int) UNIT_M32R2_U_LOAD, 1,= 1 } } },=0A= { M32R2F_INSN_SATB, model_m32r2_satb, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SATH, model_m32r2_sath, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_SAT, model_m32r2_sat, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_PCMPBZ, model_m32r2_pcmpbz, { { (int) UNIT_M32R2_U_CMP, 1, = 1 } } },=0A= { M32R2F_INSN_SADD, model_m32r2_sadd, { { (int) UNIT_M32R2_U_MAC, 1, 1 } = } },=0A= { M32R2F_INSN_MACWU1, model_m32r2_macwu1, { { (int) UNIT_M32R2_U_MAC, 1, = 1 } } },=0A= { M32R2F_INSN_MSBLO, model_m32r2_msblo, { { (int) UNIT_M32R2_U_MAC, 1, 1 = } } },=0A= { M32R2F_INSN_MULWU1, model_m32r2_mulwu1, { { (int) UNIT_M32R2_U_MAC, 1, = 1 } } },=0A= { M32R2F_INSN_MACLH1, model_m32r2_maclh1, { { (int) UNIT_M32R2_U_MAC, 1, = 1 } } },=0A= { M32R2F_INSN_SC, model_m32r2_sc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } } }= ,=0A= { M32R2F_INSN_SNC, model_m32r2_snc, { { (int) UNIT_M32R2_U_EXEC, 1, 1 } }= },=0A= { M32R2F_INSN_CLRPSW, model_m32r2_clrpsw, { { (int) UNIT_M32R2_U_EXEC, 1,= 1 } } },=0A= { M32R2F_INSN_SETPSW, model_m32r2_setpsw, { { (int) UNIT_M32R2_U_EXEC, 1,= 1 } } },=0A= { M32R2F_INSN_BSET, model_m32r2_bset, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_BCLR, model_m32r2_bclr, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= { M32R2F_INSN_BTST, model_m32r2_btst, { { (int) UNIT_M32R2_U_EXEC, 1, 1 }= } },=0A= };=0A= =0A= #endif /* WITH_PROFILE_MODEL_P */=0A= =0A= static void=0A= m32r2_model_init (SIM_CPU *cpu)=0A= {=0A= CPU_MODEL_DATA (cpu) =3D (void *) zalloc (sizeof (MODEL_M32R2_DATA));=0A= }=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= #define TIMING_DATA(td) td=0A= #else=0A= #define TIMING_DATA(td) 0=0A= #endif=0A= =0A= static const MODEL m32r2_models[] =3D=0A= {=0A= { "m32r2", & m32r2_mach, MODEL_M32R2, TIMING_DATA (& m32r2_timing[0]), m3= 2r2_model_init },=0A= { 0 }=0A= };=0A= =0A= /* The properties of this cpu's implementation. */=0A= =0A= static const MACH_IMP_PROPERTIES m32r2f_imp_properties =3D=0A= {=0A= sizeof (SIM_CPU),=0A= #if WITH_SCACHE=0A= sizeof (SCACHE)=0A= #else=0A= 0=0A= #endif=0A= };=0A= =0A= =0A= static void=0A= m32r2f_prepare_run (SIM_CPU *cpu)=0A= {=0A= if (CPU_IDESC (cpu) =3D=3D NULL)=0A= m32r2f_init_idesc_table (cpu);=0A= }=0A= =0A= static const CGEN_INSN *=0A= m32r2f_get_idata (SIM_CPU *cpu, int inum)=0A= {=0A= return CPU_IDESC (cpu) [inum].idata;=0A= }=0A= =0A= static void=0A= m32r2_init_cpu (SIM_CPU *cpu)=0A= {=0A= CPU_REG_FETCH (cpu) =3D m32r2f_fetch_register;=0A= CPU_REG_STORE (cpu) =3D m32r2f_store_register;=0A= CPU_PC_FETCH (cpu) =3D m32r2f_h_pc_get;=0A= CPU_PC_STORE (cpu) =3D m32r2f_h_pc_set;=0A= CPU_GET_IDATA (cpu) =3D m32r2f_get_idata;=0A= CPU_MAX_INSNS (cpu) =3D M32R2F_INSN__MAX;=0A= CPU_INSN_NAME (cpu) =3D cgen_insn_name;=0A= CPU_FULL_ENGINE_FN (cpu) =3D m32r2f_engine_run_full;=0A= #if WITH_FAST=0A= CPU_FAST_ENGINE_FN (cpu) =3D m32r2f_engine_run_fast;=0A= #else=0A= CPU_FAST_ENGINE_FN (cpu) =3D m32r2f_engine_run_full;=0A= #endif=0A= }=0A= =0A= const MACH m32r2_mach =3D=0A= {=0A= "m32r2", "m32r2", MACH_M32R2,=0A= 32, 32, & m32r2_models[0], & m32r2f_imp_properties,=0A= m32r2_init_cpu,=0A= m32r2f_prepare_run=0A= };=0A= =0A= --Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ) Content-type: application/octet-stream; name=cpu2.c Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=cpu2.c Content-length: 4271 /* Misc. support for CPU family m32r2f.=0A= =0A= THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= =0A= Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foun= dation, Inc.=0A= =0A= This file is part of the GNU simulators.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= */=0A= =0A= #define WANT_CPU m32r2f=0A= #define WANT_CPU_M32R2F=0A= =0A= #include "sim-main.h"=0A= #include "cgen-ops.h"=0A= =0A= /* Get the value of h-pc. */=0A= =0A= USI=0A= m32r2f_h_pc_get (SIM_CPU *current_cpu)=0A= {=0A= return CPU (h_pc);=0A= }=0A= =0A= /* Set a value for h-pc. */=0A= =0A= void=0A= m32r2f_h_pc_set (SIM_CPU *current_cpu, USI newval)=0A= {=0A= CPU (h_pc) =3D newval;=0A= }=0A= =0A= /* Get the value of h-gr. */=0A= =0A= SI=0A= m32r2f_h_gr_get (SIM_CPU *current_cpu, UINT regno)=0A= {=0A= return CPU (h_gr[regno]);=0A= }=0A= =0A= /* Set a value for h-gr. */=0A= =0A= void=0A= m32r2f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)=0A= {=0A= CPU (h_gr[regno]) =3D newval;=0A= }=0A= =0A= /* Get the value of h-cr. */=0A= =0A= USI=0A= m32r2f_h_cr_get (SIM_CPU *current_cpu, UINT regno)=0A= {=0A= return GET_H_CR (regno);=0A= }=0A= =0A= /* Set a value for h-cr. */=0A= =0A= void=0A= m32r2f_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)=0A= {=0A= SET_H_CR (regno, newval);=0A= }=0A= =0A= /* Get the value of h-accum. */=0A= =0A= DI=0A= m32r2f_h_accum_get (SIM_CPU *current_cpu)=0A= {=0A= return GET_H_ACCUM ();=0A= }=0A= =0A= /* Set a value for h-accum. */=0A= =0A= void=0A= m32r2f_h_accum_set (SIM_CPU *current_cpu, DI newval)=0A= {=0A= SET_H_ACCUM (newval);=0A= }=0A= =0A= /* Get the value of h-accums. */=0A= =0A= DI=0A= m32r2f_h_accums_get (SIM_CPU *current_cpu, UINT regno)=0A= {=0A= return GET_H_ACCUMS (regno);=0A= }=0A= =0A= /* Set a value for h-accums. */=0A= =0A= void=0A= m32r2f_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)=0A= {=0A= SET_H_ACCUMS (regno, newval);=0A= }=0A= =0A= /* Get the value of h-cond. */=0A= =0A= BI=0A= m32r2f_h_cond_get (SIM_CPU *current_cpu)=0A= {=0A= return CPU (h_cond);=0A= }=0A= =0A= /* Set a value for h-cond. */=0A= =0A= void=0A= m32r2f_h_cond_set (SIM_CPU *current_cpu, BI newval)=0A= {=0A= CPU (h_cond) =3D newval;=0A= }=0A= =0A= /* Get the value of h-psw. */=0A= =0A= UQI=0A= m32r2f_h_psw_get (SIM_CPU *current_cpu)=0A= {=0A= return GET_H_PSW ();=0A= }=0A= =0A= /* Set a value for h-psw. */=0A= =0A= void=0A= m32r2f_h_psw_set (SIM_CPU *current_cpu, UQI newval)=0A= {=0A= SET_H_PSW (newval);=0A= }=0A= =0A= /* Get the value of h-bpsw. */=0A= =0A= UQI=0A= m32r2f_h_bpsw_get (SIM_CPU *current_cpu)=0A= {=0A= return CPU (h_bpsw);=0A= }=0A= =0A= /* Set a value for h-bpsw. */=0A= =0A= void=0A= m32r2f_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)=0A= {=0A= CPU (h_bpsw) =3D newval;=0A= }=0A= =0A= /* Get the value of h-bbpsw. */=0A= =0A= UQI=0A= m32r2f_h_bbpsw_get (SIM_CPU *current_cpu)=0A= {=0A= return CPU (h_bbpsw);=0A= }=0A= =0A= /* Set a value for h-bbpsw. */=0A= =0A= void=0A= m32r2f_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)=0A= {=0A= CPU (h_bbpsw) =3D newval;=0A= }=0A= =0A= /* Get the value of h-lock. */=0A= =0A= BI=0A= m32r2f_h_lock_get (SIM_CPU *current_cpu)=0A= {=0A= return CPU (h_lock);=0A= }=0A= =0A= /* Set a value for h-lock. */=0A= =0A= void=0A= m32r2f_h_lock_set (SIM_CPU *current_cpu, BI newval)=0A= {=0A= CPU (h_lock) =3D newval;=0A= }=0A= =0A= /* Record trace results for INSN. */=0A= =0A= void=0A= m32r2f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,=0A= int *indices, TRACE_RECORD *tr)=0A= {=0A= }=0A= --Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ) Content-type: application/octet-stream; name=cpu2.h Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=cpu2.h Content-length: 32016 /* CPU family header for m32r2f.=0A= =0A= THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= =0A= Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foun= dation, Inc.=0A= =0A= This file is part of the GNU simulators.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= */=0A= =0A= #ifndef CPU_M32R2F_H=0A= #define CPU_M32R2F_H=0A= =0A= /* Maximum number of instructions that are fetched at a time.=0A= This is for LIW type instructions sets (e.g. m32r). */=0A= #define MAX_LIW_INSNS 2=0A= =0A= /* Maximum number of instructions that can be executed in parallel. */=0A= #define MAX_PARALLEL_INSNS 2=0A= =0A= /* CPU state information. */=0A= typedef struct {=0A= /* Hardware elements. */=0A= struct {=0A= /* program counter */=0A= USI h_pc;=0A= #define GET_H_PC() CPU (h_pc)=0A= #define SET_H_PC(x) (CPU (h_pc) =3D (x))=0A= /* general registers */=0A= SI h_gr[16];=0A= #define GET_H_GR(a1) CPU (h_gr)[a1]=0A= #define SET_H_GR(a1, x) (CPU (h_gr)[a1] =3D (x))=0A= /* control registers */=0A= USI h_cr[16];=0A= #define GET_H_CR(index) m32r2f_h_cr_get_handler (current_cpu, index)=0A= #define SET_H_CR(index, x) \=0A= do { \=0A= m32r2f_h_cr_set_handler (current_cpu, (index), (x));\=0A= ;} while (0)=0A= /* accumulator */=0A= DI h_accum;=0A= #define GET_H_ACCUM() m32r2f_h_accum_get_handler (current_cpu)=0A= #define SET_H_ACCUM(x) \=0A= do { \=0A= m32r2f_h_accum_set_handler (current_cpu, (x));\=0A= ;} while (0)=0A= /* accumulators */=0A= DI h_accums[2];=0A= #define GET_H_ACCUMS(index) m32r2f_h_accums_get_handler (current_cpu, index= )=0A= #define SET_H_ACCUMS(index, x) \=0A= do { \=0A= m32r2f_h_accums_set_handler (current_cpu, (index), (x));\=0A= ;} while (0)=0A= /* condition bit */=0A= BI h_cond;=0A= #define GET_H_COND() CPU (h_cond)=0A= #define SET_H_COND(x) (CPU (h_cond) =3D (x))=0A= /* psw part of psw */=0A= UQI h_psw;=0A= #define GET_H_PSW() m32r2f_h_psw_get_handler (current_cpu)=0A= #define SET_H_PSW(x) \=0A= do { \=0A= m32r2f_h_psw_set_handler (current_cpu, (x));\=0A= ;} while (0)=0A= /* backup psw */=0A= UQI h_bpsw;=0A= #define GET_H_BPSW() CPU (h_bpsw)=0A= #define SET_H_BPSW(x) (CPU (h_bpsw) =3D (x))=0A= /* backup bpsw */=0A= UQI h_bbpsw;=0A= #define GET_H_BBPSW() CPU (h_bbpsw)=0A= #define SET_H_BBPSW(x) (CPU (h_bbpsw) =3D (x))=0A= /* lock */=0A= BI h_lock;=0A= #define GET_H_LOCK() CPU (h_lock)=0A= #define SET_H_LOCK(x) (CPU (h_lock) =3D (x))=0A= } hardware;=0A= #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)=0A= } M32R2F_CPU_DATA;=0A= =0A= /* Cover fns for register access. */=0A= USI m32r2f_h_pc_get (SIM_CPU *);=0A= void m32r2f_h_pc_set (SIM_CPU *, USI);=0A= SI m32r2f_h_gr_get (SIM_CPU *, UINT);=0A= void m32r2f_h_gr_set (SIM_CPU *, UINT, SI);=0A= USI m32r2f_h_cr_get (SIM_CPU *, UINT);=0A= void m32r2f_h_cr_set (SIM_CPU *, UINT, USI);=0A= DI m32r2f_h_accum_get (SIM_CPU *);=0A= void m32r2f_h_accum_set (SIM_CPU *, DI);=0A= DI m32r2f_h_accums_get (SIM_CPU *, UINT);=0A= void m32r2f_h_accums_set (SIM_CPU *, UINT, DI);=0A= BI m32r2f_h_cond_get (SIM_CPU *);=0A= void m32r2f_h_cond_set (SIM_CPU *, BI);=0A= UQI m32r2f_h_psw_get (SIM_CPU *);=0A= void m32r2f_h_psw_set (SIM_CPU *, UQI);=0A= UQI m32r2f_h_bpsw_get (SIM_CPU *);=0A= void m32r2f_h_bpsw_set (SIM_CPU *, UQI);=0A= UQI m32r2f_h_bbpsw_get (SIM_CPU *);=0A= void m32r2f_h_bbpsw_set (SIM_CPU *, UQI);=0A= BI m32r2f_h_lock_get (SIM_CPU *);=0A= void m32r2f_h_lock_set (SIM_CPU *, BI);=0A= =0A= /* These must be hand-written. */=0A= extern CPUREG_FETCH_FN m32r2f_fetch_register;=0A= extern CPUREG_STORE_FN m32r2f_store_register;=0A= =0A= typedef struct {=0A= int empty;=0A= } MODEL_M32R2_DATA;=0A= =0A= /* Instruction argument buffer. */=0A= =0A= union sem_fields {=0A= struct { /* no operands */=0A= int empty;=0A= } fmt_empty;=0A= struct { /* */=0A= UINT f_uimm8;=0A= } sfmt_clrpsw;=0A= struct { /* */=0A= UINT f_uimm4;=0A= } sfmt_trap;=0A= struct { /* */=0A= IADDR i_disp24;=0A= unsigned char out_h_gr_SI_14;=0A= } sfmt_bl24;=0A= struct { /* */=0A= IADDR i_disp8;=0A= unsigned char out_h_gr_SI_14;=0A= } sfmt_bl8;=0A= struct { /* */=0A= SI f_imm1;=0A= UINT f_accd;=0A= UINT f_accs;=0A= } sfmt_rac_dsi;=0A= struct { /* */=0A= SI* i_dr;=0A= UINT f_hi16;=0A= UINT f_r1;=0A= unsigned char out_dr;=0A= } sfmt_seth;=0A= struct { /* */=0A= SI* i_src1;=0A= UINT f_accs;=0A= UINT f_r1;=0A= unsigned char in_src1;=0A= } sfmt_mvtachi_a;=0A= struct { /* */=0A= SI* i_dr;=0A= UINT f_accs;=0A= UINT f_r1;=0A= unsigned char out_dr;=0A= } sfmt_mvfachi_a;=0A= struct { /* */=0A= ADDR i_uimm24;=0A= SI* i_dr;=0A= UINT f_r1;=0A= unsigned char out_dr;=0A= } sfmt_ld24;=0A= struct { /* */=0A= SI* i_sr;=0A= UINT f_r2;=0A= unsigned char in_sr;=0A= unsigned char out_h_gr_SI_14;=0A= } sfmt_jl;=0A= struct { /* */=0A= SI* i_sr;=0A= INT f_simm16;=0A= UINT f_r2;=0A= UINT f_uimm3;=0A= unsigned char in_sr;=0A= } sfmt_bset;=0A= struct { /* */=0A= SI* i_dr;=0A= UINT f_r1;=0A= UINT f_uimm5;=0A= unsigned char in_dr;=0A= unsigned char out_dr;=0A= } sfmt_slli;=0A= struct { /* */=0A= SI* i_dr;=0A= INT f_simm8;=0A= UINT f_r1;=0A= unsigned char in_dr;=0A= unsigned char out_dr;=0A= } sfmt_addi;=0A= struct { /* */=0A= SI* i_src1;=0A= SI* i_src2;=0A= UINT f_r1;=0A= UINT f_r2;=0A= unsigned char in_src1;=0A= unsigned char in_src2;=0A= unsigned char out_src2;=0A= } sfmt_st_plus;=0A= struct { /* */=0A= SI* i_src1;=0A= SI* i_src2;=0A= INT f_simm16;=0A= UINT f_r1;=0A= UINT f_r2;=0A= unsigned char in_src1;=0A= unsigned char in_src2;=0A= } sfmt_st_d;=0A= struct { /* */=0A= SI* i_src1;=0A= SI* i_src2;=0A= UINT f_acc;=0A= UINT f_r1;=0A= UINT f_r2;=0A= unsigned char in_src1;=0A= unsigned char in_src2;=0A= } sfmt_machi_a;=0A= struct { /* */=0A= SI* i_dr;=0A= SI* i_sr;=0A= UINT f_r1;=0A= UINT f_r2;=0A= unsigned char in_sr;=0A= unsigned char out_dr;=0A= unsigned char out_sr;=0A= } sfmt_ld_plus;=0A= struct { /* */=0A= IADDR i_disp16;=0A= SI* i_src1;=0A= SI* i_src2;=0A= UINT f_r1;=0A= UINT f_r2;=0A= unsigned char in_src1;=0A= unsigned char in_src2;=0A= } sfmt_beq;=0A= struct { /* */=0A= SI* i_dr;=0A= SI* i_sr;=0A= UINT f_r1;=0A= UINT f_r2;=0A= UINT f_uimm16;=0A= unsigned char in_sr;=0A= unsigned char out_dr;=0A= } sfmt_and3;=0A= struct { /* */=0A= SI* i_dr;=0A= SI* i_sr;=0A= INT f_simm16;=0A= UINT f_r1;=0A= UINT f_r2;=0A= unsigned char in_sr;=0A= unsigned char out_dr;=0A= } sfmt_add3;=0A= struct { /* */=0A= SI* i_dr;=0A= SI* i_sr;=0A= UINT f_r1;=0A= UINT f_r2;=0A= unsigned char in_dr;=0A= unsigned char in_sr;=0A= unsigned char out_dr;=0A= } sfmt_add;=0A= #if WITH_SCACHE_PBB=0A= /* Writeback handler. */=0A= struct {=0A= /* Pointer to argbuf entry for insn whose results need writing back. *= /=0A= const struct argbuf *abuf;=0A= } write;=0A= /* x-before handler */=0A= struct {=0A= /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/=0A= int first_p;=0A= } before;=0A= /* x-after handler */=0A= struct {=0A= int empty;=0A= } after;=0A= /* This entry is used to terminate each pbb. */=0A= struct {=0A= /* Number of insns in pbb. */=0A= int insn_count;=0A= /* Next pbb to execute. */=0A= SCACHE *next;=0A= SCACHE *branch_target;=0A= } chain;=0A= #endif=0A= };=0A= =0A= /* The ARGBUF struct. */=0A= struct argbuf {=0A= /* These are the baseclass definitions. */=0A= IADDR addr;=0A= const IDESC *idesc;=0A= char trace_p;=0A= char profile_p;=0A= /* ??? Temporary hack for skip insns. */=0A= char skip_count;=0A= char unused;=0A= /* cpu specific data follows */=0A= union sem semantic;=0A= int written;=0A= union sem_fields fields;=0A= };=0A= =0A= /* A cached insn.=0A= =0A= ??? SCACHE used to contain more than just argbuf. We could delete the= =0A= type entirely and always just use ARGBUF, but for future concerns and as= =0A= a level of abstraction it is left in. */=0A= =0A= struct scache {=0A= struct argbuf argbuf;=0A= };=0A= =0A= /* Macros to simplify extraction, reading and semantic code.=0A= These define and assign the local vars that contain the insn's fields. = */=0A= =0A= #define EXTRACT_IFMT_EMPTY_VARS \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_EMPTY_CODE \=0A= length =3D 0; \=0A= =0A= #define EXTRACT_IFMT_ADD_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_ADD_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_ADD3_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= INT f_simm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_ADD3_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_AND3_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= UINT f_uimm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_AND3_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_uimm16 =3D EXTRACT_MSB0_UINT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_OR3_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= UINT f_uimm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_OR3_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_uimm16 =3D EXTRACT_MSB0_UINT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_ADDI_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= INT f_simm8; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_ADDI_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_simm8 =3D EXTRACT_MSB0_INT (insn, 16, 8, 8); \=0A= =0A= #define EXTRACT_IFMT_ADDV3_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= INT f_simm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_ADDV3_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_BC8_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= SI f_disp8; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_BC8_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_disp8 =3D ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-= 4)))); \=0A= =0A= #define EXTRACT_IFMT_BC24_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= SI f_disp24; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_BC24_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_disp24 =3D ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \= =0A= =0A= #define EXTRACT_IFMT_BEQ_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= SI f_disp16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_BEQ_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_disp16 =3D ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \= =0A= =0A= #define EXTRACT_IFMT_BEQZ_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= SI f_disp16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_BEQZ_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_disp16 =3D ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \= =0A= =0A= #define EXTRACT_IFMT_CMP_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_CMP_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_CMPI_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= INT f_simm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_CMPI_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_CMPZ_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_CMPZ_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_DIV_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= INT f_simm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_DIV_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_JC_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_JC_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_LD24_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_uimm24; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_LD24_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_uimm24 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 24); \=0A= =0A= #define EXTRACT_IFMT_LDI16_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= INT f_simm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_LDI16_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_MACHI_A_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_acc; \=0A= UINT f_op23; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_MACHI_A_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_acc =3D EXTRACT_MSB0_UINT (insn, 16, 8, 1); \=0A= f_op23 =3D EXTRACT_MSB0_UINT (insn, 16, 9, 3); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_MVFACHI_A_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_accs; \=0A= UINT f_op3; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_MVFACHI_A_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_accs =3D EXTRACT_MSB0_UINT (insn, 16, 12, 2); \=0A= f_op3 =3D EXTRACT_MSB0_UINT (insn, 16, 14, 2); \=0A= =0A= #define EXTRACT_IFMT_MVFC_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_MVFC_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_MVTACHI_A_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_accs; \=0A= UINT f_op3; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_MVTACHI_A_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_accs =3D EXTRACT_MSB0_UINT (insn, 16, 12, 2); \=0A= f_op3 =3D EXTRACT_MSB0_UINT (insn, 16, 14, 2); \=0A= =0A= #define EXTRACT_IFMT_MVTC_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_MVTC_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_NOP_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_NOP_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_RAC_DSI_VARS \=0A= UINT f_op1; \=0A= UINT f_accd; \=0A= UINT f_bits67; \=0A= UINT f_op2; \=0A= UINT f_accs; \=0A= UINT f_bit14; \=0A= SI f_imm1; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_RAC_DSI_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_accd =3D EXTRACT_MSB0_UINT (insn, 16, 4, 2); \=0A= f_bits67 =3D EXTRACT_MSB0_UINT (insn, 16, 6, 2); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_accs =3D EXTRACT_MSB0_UINT (insn, 16, 12, 2); \=0A= f_bit14 =3D EXTRACT_MSB0_UINT (insn, 16, 14, 1); \=0A= f_imm1 =3D ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \=0A= =0A= #define EXTRACT_IFMT_SETH_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= UINT f_hi16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_SETH_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_hi16 =3D EXTRACT_MSB0_UINT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_SLLI_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_shift_op2; \=0A= UINT f_uimm5; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_SLLI_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_shift_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 3); \=0A= f_uimm5 =3D EXTRACT_MSB0_UINT (insn, 16, 11, 5); \=0A= =0A= #define EXTRACT_IFMT_ST_D_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= INT f_simm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_ST_D_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_TRAP_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_uimm4; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_TRAP_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_uimm4 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= #define EXTRACT_IFMT_SATB_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= UINT f_uimm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_SATB_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_uimm16 =3D EXTRACT_MSB0_UINT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_CLRPSW_VARS \=0A= UINT f_op1; \=0A= UINT f_r1; \=0A= UINT f_uimm8; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_CLRPSW_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4); \=0A= f_uimm8 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 8); \=0A= =0A= #define EXTRACT_IFMT_BSET_VARS \=0A= UINT f_op1; \=0A= UINT f_bit4; \=0A= UINT f_uimm3; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= INT f_simm16; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_BSET_CODE \=0A= length =3D 4; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 32, 0, 4); \=0A= f_bit4 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 1); \=0A= f_uimm3 =3D EXTRACT_MSB0_UINT (insn, 32, 5, 3); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4); \=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16); \=0A= =0A= #define EXTRACT_IFMT_BTST_VARS \=0A= UINT f_op1; \=0A= UINT f_bit4; \=0A= UINT f_uimm3; \=0A= UINT f_op2; \=0A= UINT f_r2; \=0A= unsigned int length;=0A= #define EXTRACT_IFMT_BTST_CODE \=0A= length =3D 2; \=0A= f_op1 =3D EXTRACT_MSB0_UINT (insn, 16, 0, 4); \=0A= f_bit4 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 1); \=0A= f_uimm3 =3D EXTRACT_MSB0_UINT (insn, 16, 5, 3); \=0A= f_op2 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 4); \=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4); \=0A= =0A= /* Queued output values of an instruction. */=0A= =0A= struct parexec {=0A= union {=0A= struct { /* empty sformat for unspecified field list */=0A= int empty;=0A= } sfmt_empty;=0A= struct { /* e.g. add $dr,$sr */=0A= SI dr;=0A= } sfmt_add;=0A= struct { /* e.g. add3 $dr,$sr,$hash$slo16 */=0A= SI dr;=0A= } sfmt_add3;=0A= struct { /* e.g. and3 $dr,$sr,$uimm16 */=0A= SI dr;=0A= } sfmt_and3;=0A= struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */=0A= SI dr;=0A= } sfmt_or3;=0A= struct { /* e.g. addi $dr,$simm8 */=0A= SI dr;=0A= } sfmt_addi;=0A= struct { /* e.g. addv $dr,$sr */=0A= BI condbit;=0A= SI dr;=0A= } sfmt_addv;=0A= struct { /* e.g. addv3 $dr,$sr,$simm16 */=0A= BI condbit;=0A= SI dr;=0A= } sfmt_addv3;=0A= struct { /* e.g. addx $dr,$sr */=0A= BI condbit;=0A= SI dr;=0A= } sfmt_addx;=0A= struct { /* e.g. bc.s $disp8 */=0A= USI pc;=0A= } sfmt_bc8;=0A= struct { /* e.g. bc.l $disp24 */=0A= USI pc;=0A= } sfmt_bc24;=0A= struct { /* e.g. beq $src1,$src2,$disp16 */=0A= USI pc;=0A= } sfmt_beq;=0A= struct { /* e.g. beqz $src2,$disp16 */=0A= USI pc;=0A= } sfmt_beqz;=0A= struct { /* e.g. bl.s $disp8 */=0A= SI h_gr_SI_14;=0A= USI pc;=0A= } sfmt_bl8;=0A= struct { /* e.g. bl.l $disp24 */=0A= SI h_gr_SI_14;=0A= USI pc;=0A= } sfmt_bl24;=0A= struct { /* e.g. bcl.s $disp8 */=0A= SI h_gr_SI_14;=0A= USI pc;=0A= } sfmt_bcl8;=0A= struct { /* e.g. bcl.l $disp24 */=0A= SI h_gr_SI_14;=0A= USI pc;=0A= } sfmt_bcl24;=0A= struct { /* e.g. bra.s $disp8 */=0A= USI pc;=0A= } sfmt_bra8;=0A= struct { /* e.g. bra.l $disp24 */=0A= USI pc;=0A= } sfmt_bra24;=0A= struct { /* e.g. cmp $src1,$src2 */=0A= BI condbit;=0A= } sfmt_cmp;=0A= struct { /* e.g. cmpi $src2,$simm16 */=0A= BI condbit;=0A= } sfmt_cmpi;=0A= struct { /* e.g. cmpz $src2 */=0A= BI condbit;=0A= } sfmt_cmpz;=0A= struct { /* e.g. div $dr,$sr */=0A= SI dr;=0A= } sfmt_div;=0A= struct { /* e.g. jc $sr */=0A= USI pc;=0A= } sfmt_jc;=0A= struct { /* e.g. jl $sr */=0A= SI h_gr_SI_14;=0A= USI pc;=0A= } sfmt_jl;=0A= struct { /* e.g. jmp $sr */=0A= USI pc;=0A= } sfmt_jmp;=0A= struct { /* e.g. ld $dr,@$sr */=0A= SI dr;=0A= } sfmt_ld;=0A= struct { /* e.g. ld $dr,@($slo16,$sr) */=0A= SI dr;=0A= } sfmt_ld_d;=0A= struct { /* e.g. ldb $dr,@$sr */=0A= SI dr;=0A= } sfmt_ldb;=0A= struct { /* e.g. ldb $dr,@($slo16,$sr) */=0A= SI dr;=0A= } sfmt_ldb_d;=0A= struct { /* e.g. ldh $dr,@$sr */=0A= SI dr;=0A= } sfmt_ldh;=0A= struct { /* e.g. ldh $dr,@($slo16,$sr) */=0A= SI dr;=0A= } sfmt_ldh_d;=0A= struct { /* e.g. ld $dr,@$sr+ */=0A= SI dr;=0A= SI sr;=0A= } sfmt_ld_plus;=0A= struct { /* e.g. ld24 $dr,$uimm24 */=0A= SI dr;=0A= } sfmt_ld24;=0A= struct { /* e.g. ldi8 $dr,$simm8 */=0A= SI dr;=0A= } sfmt_ldi8;=0A= struct { /* e.g. ldi16 $dr,$hash$slo16 */=0A= SI dr;=0A= } sfmt_ldi16;=0A= struct { /* e.g. lock $dr,@$sr */=0A= SI dr;=0A= BI h_lock_BI;=0A= } sfmt_lock;=0A= struct { /* e.g. machi $src1,$src2,$acc */=0A= DI acc;=0A= } sfmt_machi_a;=0A= struct { /* e.g. mulhi $src1,$src2,$acc */=0A= DI acc;=0A= } sfmt_mulhi_a;=0A= struct { /* e.g. mv $dr,$sr */=0A= SI dr;=0A= } sfmt_mv;=0A= struct { /* e.g. mvfachi $dr,$accs */=0A= SI dr;=0A= } sfmt_mvfachi_a;=0A= struct { /* e.g. mvfc $dr,$scr */=0A= SI dr;=0A= } sfmt_mvfc;=0A= struct { /* e.g. mvtachi $src1,$accs */=0A= DI accs;=0A= } sfmt_mvtachi_a;=0A= struct { /* e.g. mvtc $sr,$dcr */=0A= USI dcr;=0A= } sfmt_mvtc;=0A= struct { /* e.g. nop */=0A= int empty;=0A= } sfmt_nop;=0A= struct { /* e.g. rac $accd,$accs,$imm1 */=0A= DI accd;=0A= } sfmt_rac_dsi;=0A= struct { /* e.g. rte */=0A= UQI h_bpsw_UQI;=0A= USI h_cr_USI_6;=0A= UQI h_psw_UQI;=0A= USI pc;=0A= } sfmt_rte;=0A= struct { /* e.g. seth $dr,$hash$hi16 */=0A= SI dr;=0A= } sfmt_seth;=0A= struct { /* e.g. sll3 $dr,$sr,$simm16 */=0A= SI dr;=0A= } sfmt_sll3;=0A= struct { /* e.g. slli $dr,$uimm5 */=0A= SI dr;=0A= } sfmt_slli;=0A= struct { /* e.g. st $src1,@$src2 */=0A= SI h_memory_SI_src2;=0A= USI h_memory_SI_src2_idx;=0A= } sfmt_st;=0A= struct { /* e.g. st $src1,@($slo16,$src2) */=0A= SI h_memory_SI_add__DFLT_src2_slo16;=0A= USI h_memory_SI_add__DFLT_src2_slo16_idx;=0A= } sfmt_st_d;=0A= struct { /* e.g. stb $src1,@$src2 */=0A= QI h_memory_QI_src2;=0A= USI h_memory_QI_src2_idx;=0A= } sfmt_stb;=0A= struct { /* e.g. stb $src1,@($slo16,$src2) */=0A= QI h_memory_QI_add__DFLT_src2_slo16;=0A= USI h_memory_QI_add__DFLT_src2_slo16_idx;=0A= } sfmt_stb_d;=0A= struct { /* e.g. sth $src1,@$src2 */=0A= HI h_memory_HI_src2;=0A= USI h_memory_HI_src2_idx;=0A= } sfmt_sth;=0A= struct { /* e.g. sth $src1,@($slo16,$src2) */=0A= HI h_memory_HI_add__DFLT_src2_slo16;=0A= USI h_memory_HI_add__DFLT_src2_slo16_idx;=0A= } sfmt_sth_d;=0A= struct { /* e.g. st $src1,@+$src2 */=0A= SI h_memory_SI_new_src2;=0A= USI h_memory_SI_new_src2_idx;=0A= SI src2;=0A= } sfmt_st_plus;=0A= struct { /* e.g. sth $src1,@$src2+ */=0A= HI h_memory_HI_new_src2;=0A= USI h_memory_HI_new_src2_idx;=0A= SI src2;=0A= } sfmt_sth_plus;=0A= struct { /* e.g. stb $src1,@$src2+ */=0A= QI h_memory_QI_new_src2;=0A= USI h_memory_QI_new_src2_idx;=0A= SI src2;=0A= } sfmt_stb_plus;=0A= struct { /* e.g. trap $uimm4 */=0A= UQI h_bbpsw_UQI;=0A= UQI h_bpsw_UQI;=0A= USI h_cr_USI_14;=0A= USI h_cr_USI_6;=0A= UQI h_psw_UQI;=0A= SI pc;=0A= } sfmt_trap;=0A= struct { /* e.g. unlock $src1,@$src2 */=0A= BI h_lock_BI;=0A= SI h_memory_SI_src2;=0A= USI h_memory_SI_src2_idx;=0A= } sfmt_unlock;=0A= struct { /* e.g. satb $dr,$sr */=0A= SI dr;=0A= } sfmt_satb;=0A= struct { /* e.g. sat $dr,$sr */=0A= SI dr;=0A= } sfmt_sat;=0A= struct { /* e.g. sadd */=0A= DI h_accums_DI_0;=0A= } sfmt_sadd;=0A= struct { /* e.g. macwu1 $src1,$src2 */=0A= DI h_accums_DI_1;=0A= } sfmt_macwu1;=0A= struct { /* e.g. msblo $src1,$src2 */=0A= DI accum;=0A= } sfmt_msblo;=0A= struct { /* e.g. mulwu1 $src1,$src2 */=0A= DI h_accums_DI_1;=0A= } sfmt_mulwu1;=0A= struct { /* e.g. sc */=0A= int empty;=0A= } sfmt_sc;=0A= struct { /* e.g. clrpsw $uimm8 */=0A= USI h_cr_USI_0;=0A= } sfmt_clrpsw;=0A= struct { /* e.g. setpsw $uimm8 */=0A= USI h_cr_USI_0;=0A= } sfmt_setpsw;=0A= struct { /* e.g. bset $uimm3,@($slo16,$sr) */=0A= QI h_memory_QI_add__DFLT_sr_slo16;=0A= USI h_memory_QI_add__DFLT_sr_slo16_idx;=0A= } sfmt_bset;=0A= struct { /* e.g. btst $uimm3,$sr */=0A= BI condbit;=0A= } sfmt_btst;=0A= } operands;=0A= /* For conditionally written operands, bitmask of which ones were. */=0A= int written;=0A= };=0A= =0A= /* Collection of various things for the trace handler to use. */=0A= =0A= typedef struct trace_record {=0A= IADDR pc;=0A= /* FIXME:wip */=0A= } TRACE_RECORD;=0A= =0A= #endif /* CPU_M32R2F_H */=0A= --Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ) Content-type: application/octet-stream; name=decode2.c Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=decode2.c Content-length: 100539 /* Simulator instruction decoder for m32r2f.=0A= =0A= THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= =0A= Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foun= dation, Inc.=0A= =0A= This file is part of the GNU simulators.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= */=0A= =0A= #define WANT_CPU m32r2f=0A= #define WANT_CPU_M32R2F=0A= =0A= #include "sim-main.h"=0A= #include "sim-assert.h"=0A= =0A= /* Insn can't be executed in parallel.=0A= Or is that "do NOt Pass to Air defense Radar"? :-) */=0A= #define NOPAR (-1)=0A= =0A= /* The instruction descriptor array.=0A= This is computed at runtime. Space for it is not malloc'd to save a=0A= teensy bit of cpu in the decoder. Moving it to malloc space is trivial= =0A= but won't be done until necessary (we don't currently support the runtim= e=0A= addition of instructions nor an SMP machine with different cpus). */=0A= static IDESC m32r2f_insn_data[M32R2F_INSN__MAX];=0A= =0A= /* Commas between elements are contained in the macros.=0A= Some of these are conditionally compiled out. */=0A= =0A= static const struct insn_sem m32r2f_insn_sem[] =3D=0A= {=0A= { VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR= , NOPAR },=0A= { VIRTUAL_INSN_X_AFTER, M32R2F_INSN_X_AFTER, M32R2F_SFMT_EMPTY, NOPAR, NO= PAR },=0A= { VIRTUAL_INSN_X_BEFORE, M32R2F_INSN_X_BEFORE, M32R2F_SFMT_EMPTY, NOPAR, = NOPAR },=0A= { VIRTUAL_INSN_X_CTI_CHAIN, M32R2F_INSN_X_CTI_CHAIN, M32R2F_SFMT_EMPTY, N= OPAR, NOPAR },=0A= { VIRTUAL_INSN_X_CHAIN, M32R2F_INSN_X_CHAIN, M32R2F_SFMT_EMPTY, NOPAR, NO= PAR },=0A= { VIRTUAL_INSN_X_BEGIN, M32R2F_INSN_X_BEGIN, M32R2F_SFMT_EMPTY, NOPAR, NO= PAR },=0A= { M32R_INSN_ADD, M32R2F_INSN_ADD, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_ADD, M= 32R2F_INSN_WRITE_ADD },=0A= { M32R_INSN_ADD3, M32R2F_INSN_ADD3, M32R2F_SFMT_ADD3, NOPAR, NOPAR },=0A= { M32R_INSN_AND, M32R2F_INSN_AND, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_AND, M= 32R2F_INSN_WRITE_AND },=0A= { M32R_INSN_AND3, M32R2F_INSN_AND3, M32R2F_SFMT_AND3, NOPAR, NOPAR },=0A= { M32R_INSN_OR, M32R2F_INSN_OR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_OR, M32R= 2F_INSN_WRITE_OR },=0A= { M32R_INSN_OR3, M32R2F_INSN_OR3, M32R2F_SFMT_OR3, NOPAR, NOPAR },=0A= { M32R_INSN_XOR, M32R2F_INSN_XOR, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_XOR, M= 32R2F_INSN_WRITE_XOR },=0A= { M32R_INSN_XOR3, M32R2F_INSN_XOR3, M32R2F_SFMT_AND3, NOPAR, NOPAR },=0A= { M32R_INSN_ADDI, M32R2F_INSN_ADDI, M32R2F_SFMT_ADDI, M32R2F_INSN_PAR_ADD= I, M32R2F_INSN_WRITE_ADDI },=0A= { M32R_INSN_ADDV, M32R2F_INSN_ADDV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_ADD= V, M32R2F_INSN_WRITE_ADDV },=0A= { M32R_INSN_ADDV3, M32R2F_INSN_ADDV3, M32R2F_SFMT_ADDV3, NOPAR, NOPAR },= =0A= { M32R_INSN_ADDX, M32R2F_INSN_ADDX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_ADD= X, M32R2F_INSN_WRITE_ADDX },=0A= { M32R_INSN_BC8, M32R2F_INSN_BC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BC8, M= 32R2F_INSN_WRITE_BC8 },=0A= { M32R_INSN_BC24, M32R2F_INSN_BC24, M32R2F_SFMT_BC24, NOPAR, NOPAR },=0A= { M32R_INSN_BEQ, M32R2F_INSN_BEQ, M32R2F_SFMT_BEQ, NOPAR, NOPAR },=0A= { M32R_INSN_BEQZ, M32R2F_INSN_BEQZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },=0A= { M32R_INSN_BGEZ, M32R2F_INSN_BGEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },=0A= { M32R_INSN_BGTZ, M32R2F_INSN_BGTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },=0A= { M32R_INSN_BLEZ, M32R2F_INSN_BLEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },=0A= { M32R_INSN_BLTZ, M32R2F_INSN_BLTZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },=0A= { M32R_INSN_BNEZ, M32R2F_INSN_BNEZ, M32R2F_SFMT_BEQZ, NOPAR, NOPAR },=0A= { M32R_INSN_BL8, M32R2F_INSN_BL8, M32R2F_SFMT_BL8, M32R2F_INSN_PAR_BL8, M= 32R2F_INSN_WRITE_BL8 },=0A= { M32R_INSN_BL24, M32R2F_INSN_BL24, M32R2F_SFMT_BL24, NOPAR, NOPAR },=0A= { M32R_INSN_BCL8, M32R2F_INSN_BCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_BCL= 8, M32R2F_INSN_WRITE_BCL8 },=0A= { M32R_INSN_BCL24, M32R2F_INSN_BCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR },= =0A= { M32R_INSN_BNC8, M32R2F_INSN_BNC8, M32R2F_SFMT_BC8, M32R2F_INSN_PAR_BNC8= , M32R2F_INSN_WRITE_BNC8 },=0A= { M32R_INSN_BNC24, M32R2F_INSN_BNC24, M32R2F_SFMT_BC24, NOPAR, NOPAR },= =0A= { M32R_INSN_BNE, M32R2F_INSN_BNE, M32R2F_SFMT_BEQ, NOPAR, NOPAR },=0A= { M32R_INSN_BRA8, M32R2F_INSN_BRA8, M32R2F_SFMT_BRA8, M32R2F_INSN_PAR_BRA= 8, M32R2F_INSN_WRITE_BRA8 },=0A= { M32R_INSN_BRA24, M32R2F_INSN_BRA24, M32R2F_SFMT_BRA24, NOPAR, NOPAR },= =0A= { M32R_INSN_BNCL8, M32R2F_INSN_BNCL8, M32R2F_SFMT_BCL8, M32R2F_INSN_PAR_B= NCL8, M32R2F_INSN_WRITE_BNCL8 },=0A= { M32R_INSN_BNCL24, M32R2F_INSN_BNCL24, M32R2F_SFMT_BCL24, NOPAR, NOPAR = },=0A= { M32R_INSN_CMP, M32R2F_INSN_CMP, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMP, M= 32R2F_INSN_WRITE_CMP },=0A= { M32R_INSN_CMPI, M32R2F_INSN_CMPI, M32R2F_SFMT_CMPI, NOPAR, NOPAR },=0A= { M32R_INSN_CMPU, M32R2F_INSN_CMPU, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CMPU= , M32R2F_INSN_WRITE_CMPU },=0A= { M32R_INSN_CMPUI, M32R2F_INSN_CMPUI, M32R2F_SFMT_CMPI, NOPAR, NOPAR },= =0A= { M32R_INSN_CMPEQ, M32R2F_INSN_CMPEQ, M32R2F_SFMT_CMP, M32R2F_INSN_PAR_CM= PEQ, M32R2F_INSN_WRITE_CMPEQ },=0A= { M32R_INSN_CMPZ, M32R2F_INSN_CMPZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR_CMP= Z, M32R2F_INSN_WRITE_CMPZ },=0A= { M32R_INSN_DIV, M32R2F_INSN_DIV, M32R2F_SFMT_DIV, NOPAR, NOPAR },=0A= { M32R_INSN_DIVU, M32R2F_INSN_DIVU, M32R2F_SFMT_DIV, NOPAR, NOPAR },=0A= { M32R_INSN_REM, M32R2F_INSN_REM, M32R2F_SFMT_DIV, NOPAR, NOPAR },=0A= { M32R_INSN_REMU, M32R2F_INSN_REMU, M32R2F_SFMT_DIV, NOPAR, NOPAR },=0A= { M32R_INSN_REMH, M32R2F_INSN_REMH, M32R2F_SFMT_DIV, NOPAR, NOPAR },=0A= { M32R_INSN_REMUH, M32R2F_INSN_REMUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },= =0A= { M32R_INSN_REMB, M32R2F_INSN_REMB, M32R2F_SFMT_DIV, NOPAR, NOPAR },=0A= { M32R_INSN_REMUB, M32R2F_INSN_REMUB, M32R2F_SFMT_DIV, NOPAR, NOPAR },= =0A= { M32R_INSN_DIVUH, M32R2F_INSN_DIVUH, M32R2F_SFMT_DIV, NOPAR, NOPAR },= =0A= { M32R_INSN_DIVB, M32R2F_INSN_DIVB, M32R2F_SFMT_DIV, NOPAR, NOPAR },=0A= { M32R_INSN_DIVUB, M32R2F_INSN_DIVUB, M32R2F_SFMT_DIV, NOPAR, NOPAR },= =0A= { M32R_INSN_DIVH, M32R2F_INSN_DIVH, M32R2F_SFMT_DIV, NOPAR, NOPAR },=0A= { M32R_INSN_JC, M32R2F_INSN_JC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JC, M32R2= F_INSN_WRITE_JC },=0A= { M32R_INSN_JNC, M32R2F_INSN_JNC, M32R2F_SFMT_JC, M32R2F_INSN_PAR_JNC, M3= 2R2F_INSN_WRITE_JNC },=0A= { M32R_INSN_JL, M32R2F_INSN_JL, M32R2F_SFMT_JL, M32R2F_INSN_PAR_JL, M32R2= F_INSN_WRITE_JL },=0A= { M32R_INSN_JMP, M32R2F_INSN_JMP, M32R2F_SFMT_JMP, M32R2F_INSN_PAR_JMP, M= 32R2F_INSN_WRITE_JMP },=0A= { M32R_INSN_LD, M32R2F_INSN_LD, M32R2F_SFMT_LD, M32R2F_INSN_PAR_LD, M32R2= F_INSN_WRITE_LD },=0A= { M32R_INSN_LD_D, M32R2F_INSN_LD_D, M32R2F_SFMT_LD_D, NOPAR, NOPAR },=0A= { M32R_INSN_LDB, M32R2F_INSN_LDB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDB, M= 32R2F_INSN_WRITE_LDB },=0A= { M32R_INSN_LDB_D, M32R2F_INSN_LDB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR },= =0A= { M32R_INSN_LDH, M32R2F_INSN_LDH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDH, M= 32R2F_INSN_WRITE_LDH },=0A= { M32R_INSN_LDH_D, M32R2F_INSN_LDH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR },= =0A= { M32R_INSN_LDUB, M32R2F_INSN_LDUB, M32R2F_SFMT_LDB, M32R2F_INSN_PAR_LDUB= , M32R2F_INSN_WRITE_LDUB },=0A= { M32R_INSN_LDUB_D, M32R2F_INSN_LDUB_D, M32R2F_SFMT_LDB_D, NOPAR, NOPAR = },=0A= { M32R_INSN_LDUH, M32R2F_INSN_LDUH, M32R2F_SFMT_LDH, M32R2F_INSN_PAR_LDUH= , M32R2F_INSN_WRITE_LDUH },=0A= { M32R_INSN_LDUH_D, M32R2F_INSN_LDUH_D, M32R2F_SFMT_LDH_D, NOPAR, NOPAR = },=0A= { M32R_INSN_LD_PLUS, M32R2F_INSN_LD_PLUS, M32R2F_SFMT_LD_PLUS, M32R2F_INS= N_PAR_LD_PLUS, M32R2F_INSN_WRITE_LD_PLUS },=0A= { M32R_INSN_LD24, M32R2F_INSN_LD24, M32R2F_SFMT_LD24, NOPAR, NOPAR },=0A= { M32R_INSN_LDI8, M32R2F_INSN_LDI8, M32R2F_SFMT_LDI8, M32R2F_INSN_PAR_LDI= 8, M32R2F_INSN_WRITE_LDI8 },=0A= { M32R_INSN_LDI16, M32R2F_INSN_LDI16, M32R2F_SFMT_LDI16, NOPAR, NOPAR },= =0A= { M32R_INSN_LOCK, M32R2F_INSN_LOCK, M32R2F_SFMT_LOCK, M32R2F_INSN_PAR_LOC= K, M32R2F_INSN_WRITE_LOCK },=0A= { M32R_INSN_MACHI_A, M32R2F_INSN_MACHI_A, M32R2F_SFMT_MACHI_A, M32R2F_INS= N_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI_A },=0A= { M32R_INSN_MACLO_A, M32R2F_INSN_MACLO_A, M32R2F_SFMT_MACHI_A, M32R2F_INS= N_PAR_MACLO_A, M32R2F_INSN_WRITE_MACLO_A },=0A= { M32R_INSN_MACWHI_A, M32R2F_INSN_MACWHI_A, M32R2F_SFMT_MACHI_A, M32R2F_I= NSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_MACWHI_A },=0A= { M32R_INSN_MACWLO_A, M32R2F_INSN_MACWLO_A, M32R2F_SFMT_MACHI_A, M32R2F_I= NSN_PAR_MACWLO_A, M32R2F_INSN_WRITE_MACWLO_A },=0A= { M32R_INSN_MUL, M32R2F_INSN_MUL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_MUL, M= 32R2F_INSN_WRITE_MUL },=0A= { M32R_INSN_MULHI_A, M32R2F_INSN_MULHI_A, M32R2F_SFMT_MULHI_A, M32R2F_INS= N_PAR_MULHI_A, M32R2F_INSN_WRITE_MULHI_A },=0A= { M32R_INSN_MULLO_A, M32R2F_INSN_MULLO_A, M32R2F_SFMT_MULHI_A, M32R2F_INS= N_PAR_MULLO_A, M32R2F_INSN_WRITE_MULLO_A },=0A= { M32R_INSN_MULWHI_A, M32R2F_INSN_MULWHI_A, M32R2F_SFMT_MULHI_A, M32R2F_I= NSN_PAR_MULWHI_A, M32R2F_INSN_WRITE_MULWHI_A },=0A= { M32R_INSN_MULWLO_A, M32R2F_INSN_MULWLO_A, M32R2F_SFMT_MULHI_A, M32R2F_I= NSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_MULWLO_A },=0A= { M32R_INSN_MV, M32R2F_INSN_MV, M32R2F_SFMT_MV, M32R2F_INSN_PAR_MV, M32R2= F_INSN_WRITE_MV },=0A= { M32R_INSN_MVFACHI_A, M32R2F_INSN_MVFACHI_A, M32R2F_SFMT_MVFACHI_A, M32R= 2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFACHI_A },=0A= { M32R_INSN_MVFACLO_A, M32R2F_INSN_MVFACLO_A, M32R2F_SFMT_MVFACHI_A, M32R= 2F_INSN_PAR_MVFACLO_A, M32R2F_INSN_WRITE_MVFACLO_A },=0A= { M32R_INSN_MVFACMI_A, M32R2F_INSN_MVFACMI_A, M32R2F_SFMT_MVFACHI_A, M32R= 2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRITE_MVFACMI_A },=0A= { M32R_INSN_MVFC, M32R2F_INSN_MVFC, M32R2F_SFMT_MVFC, M32R2F_INSN_PAR_MVF= C, M32R2F_INSN_WRITE_MVFC },=0A= { M32R_INSN_MVTACHI_A, M32R2F_INSN_MVTACHI_A, M32R2F_SFMT_MVTACHI_A, M32R= 2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVTACHI_A },=0A= { M32R_INSN_MVTACLO_A, M32R2F_INSN_MVTACLO_A, M32R2F_SFMT_MVTACHI_A, M32R= 2F_INSN_PAR_MVTACLO_A, M32R2F_INSN_WRITE_MVTACLO_A },=0A= { M32R_INSN_MVTC, M32R2F_INSN_MVTC, M32R2F_SFMT_MVTC, M32R2F_INSN_PAR_MVT= C, M32R2F_INSN_WRITE_MVTC },=0A= { M32R_INSN_NEG, M32R2F_INSN_NEG, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NEG, M3= 2R2F_INSN_WRITE_NEG },=0A= { M32R_INSN_NOP, M32R2F_INSN_NOP, M32R2F_SFMT_NOP, M32R2F_INSN_PAR_NOP, M= 32R2F_INSN_WRITE_NOP },=0A= { M32R_INSN_NOT, M32R2F_INSN_NOT, M32R2F_SFMT_MV, M32R2F_INSN_PAR_NOT, M3= 2R2F_INSN_WRITE_NOT },=0A= { M32R_INSN_RAC_DSI, M32R2F_INSN_RAC_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_INS= N_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DSI },=0A= { M32R_INSN_RACH_DSI, M32R2F_INSN_RACH_DSI, M32R2F_SFMT_RAC_DSI, M32R2F_I= NSN_PAR_RACH_DSI, M32R2F_INSN_WRITE_RACH_DSI },=0A= { M32R_INSN_RTE, M32R2F_INSN_RTE, M32R2F_SFMT_RTE, M32R2F_INSN_PAR_RTE, M= 32R2F_INSN_WRITE_RTE },=0A= { M32R_INSN_SETH, M32R2F_INSN_SETH, M32R2F_SFMT_SETH, NOPAR, NOPAR },=0A= { M32R_INSN_SLL, M32R2F_INSN_SLL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SLL, M= 32R2F_INSN_WRITE_SLL },=0A= { M32R_INSN_SLL3, M32R2F_INSN_SLL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },=0A= { M32R_INSN_SLLI, M32R2F_INSN_SLLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SLL= I, M32R2F_INSN_WRITE_SLLI },=0A= { M32R_INSN_SRA, M32R2F_INSN_SRA, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRA, M= 32R2F_INSN_WRITE_SRA },=0A= { M32R_INSN_SRA3, M32R2F_INSN_SRA3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },=0A= { M32R_INSN_SRAI, M32R2F_INSN_SRAI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRA= I, M32R2F_INSN_WRITE_SRAI },=0A= { M32R_INSN_SRL, M32R2F_INSN_SRL, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SRL, M= 32R2F_INSN_WRITE_SRL },=0A= { M32R_INSN_SRL3, M32R2F_INSN_SRL3, M32R2F_SFMT_SLL3, NOPAR, NOPAR },=0A= { M32R_INSN_SRLI, M32R2F_INSN_SRLI, M32R2F_SFMT_SLLI, M32R2F_INSN_PAR_SRL= I, M32R2F_INSN_WRITE_SRLI },=0A= { M32R_INSN_ST, M32R2F_INSN_ST, M32R2F_SFMT_ST, M32R2F_INSN_PAR_ST, M32R2= F_INSN_WRITE_ST },=0A= { M32R_INSN_ST_D, M32R2F_INSN_ST_D, M32R2F_SFMT_ST_D, NOPAR, NOPAR },=0A= { M32R_INSN_STB, M32R2F_INSN_STB, M32R2F_SFMT_STB, M32R2F_INSN_PAR_STB, M= 32R2F_INSN_WRITE_STB },=0A= { M32R_INSN_STB_D, M32R2F_INSN_STB_D, M32R2F_SFMT_STB_D, NOPAR, NOPAR },= =0A= { M32R_INSN_STH, M32R2F_INSN_STH, M32R2F_SFMT_STH, M32R2F_INSN_PAR_STH, M= 32R2F_INSN_WRITE_STH },=0A= { M32R_INSN_STH_D, M32R2F_INSN_STH_D, M32R2F_SFMT_STH_D, NOPAR, NOPAR },= =0A= { M32R_INSN_ST_PLUS, M32R2F_INSN_ST_PLUS, M32R2F_SFMT_ST_PLUS, M32R2F_INS= N_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLUS },=0A= { M32R_INSN_STH_PLUS, M32R2F_INSN_STH_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_= INSN_PAR_STH_PLUS, M32R2F_INSN_WRITE_STH_PLUS },=0A= { M32R_INSN_STB_PLUS, M32R2F_INSN_STB_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_= INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_STB_PLUS },=0A= { M32R_INSN_ST_MINUS, M32R2F_INSN_ST_MINUS, M32R2F_SFMT_ST_PLUS, M32R2F_I= NSN_PAR_ST_MINUS, M32R2F_INSN_WRITE_ST_MINUS },=0A= { M32R_INSN_SUB, M32R2F_INSN_SUB, M32R2F_SFMT_ADD, M32R2F_INSN_PAR_SUB, M= 32R2F_INSN_WRITE_SUB },=0A= { M32R_INSN_SUBV, M32R2F_INSN_SUBV, M32R2F_SFMT_ADDV, M32R2F_INSN_PAR_SUB= V, M32R2F_INSN_WRITE_SUBV },=0A= { M32R_INSN_SUBX, M32R2F_INSN_SUBX, M32R2F_SFMT_ADDX, M32R2F_INSN_PAR_SUB= X, M32R2F_INSN_WRITE_SUBX },=0A= { M32R_INSN_TRAP, M32R2F_INSN_TRAP, M32R2F_SFMT_TRAP, M32R2F_INSN_PAR_TRA= P, M32R2F_INSN_WRITE_TRAP },=0A= { M32R_INSN_UNLOCK, M32R2F_INSN_UNLOCK, M32R2F_SFMT_UNLOCK, M32R2F_INSN_P= AR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK },=0A= { M32R_INSN_SATB, M32R2F_INSN_SATB, M32R2F_SFMT_SATB, NOPAR, NOPAR },=0A= { M32R_INSN_SATH, M32R2F_INSN_SATH, M32R2F_SFMT_SATB, NOPAR, NOPAR },=0A= { M32R_INSN_SAT, M32R2F_INSN_SAT, M32R2F_SFMT_SAT, NOPAR, NOPAR },=0A= { M32R_INSN_PCMPBZ, M32R2F_INSN_PCMPBZ, M32R2F_SFMT_CMPZ, M32R2F_INSN_PAR= _PCMPBZ, M32R2F_INSN_WRITE_PCMPBZ },=0A= { M32R_INSN_SADD, M32R2F_INSN_SADD, M32R2F_SFMT_SADD, M32R2F_INSN_PAR_SAD= D, M32R2F_INSN_WRITE_SADD },=0A= { M32R_INSN_MACWU1, M32R2F_INSN_MACWU1, M32R2F_SFMT_MACWU1, M32R2F_INSN_P= AR_MACWU1, M32R2F_INSN_WRITE_MACWU1 },=0A= { M32R_INSN_MSBLO, M32R2F_INSN_MSBLO, M32R2F_SFMT_MSBLO, M32R2F_INSN_PAR_= MSBLO, M32R2F_INSN_WRITE_MSBLO },=0A= { M32R_INSN_MULWU1, M32R2F_INSN_MULWU1, M32R2F_SFMT_MULWU1, M32R2F_INSN_P= AR_MULWU1, M32R2F_INSN_WRITE_MULWU1 },=0A= { M32R_INSN_MACLH1, M32R2F_INSN_MACLH1, M32R2F_SFMT_MACWU1, M32R2F_INSN_P= AR_MACLH1, M32R2F_INSN_WRITE_MACLH1 },=0A= { M32R_INSN_SC, M32R2F_INSN_SC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SC, M32R2= F_INSN_WRITE_SC },=0A= { M32R_INSN_SNC, M32R2F_INSN_SNC, M32R2F_SFMT_SC, M32R2F_INSN_PAR_SNC, M3= 2R2F_INSN_WRITE_SNC },=0A= { M32R_INSN_CLRPSW, M32R2F_INSN_CLRPSW, M32R2F_SFMT_CLRPSW, M32R2F_INSN_P= AR_CLRPSW, M32R2F_INSN_WRITE_CLRPSW },=0A= { M32R_INSN_SETPSW, M32R2F_INSN_SETPSW, M32R2F_SFMT_SETPSW, M32R2F_INSN_P= AR_SETPSW, M32R2F_INSN_WRITE_SETPSW },=0A= { M32R_INSN_BSET, M32R2F_INSN_BSET, M32R2F_SFMT_BSET, NOPAR, NOPAR },=0A= { M32R_INSN_BCLR, M32R2F_INSN_BCLR, M32R2F_SFMT_BSET, NOPAR, NOPAR },=0A= { M32R_INSN_BTST, M32R2F_INSN_BTST, M32R2F_SFMT_BTST, M32R2F_INSN_PAR_BTS= T, M32R2F_INSN_WRITE_BTST },=0A= };=0A= =0A= static const struct insn_sem m32r2f_insn_sem_invalid =3D {=0A= VIRTUAL_INSN_X_INVALID, M32R2F_INSN_X_INVALID, M32R2F_SFMT_EMPTY, NOPAR, = NOPAR=0A= };=0A= =0A= /* Initialize an IDESC from the compile-time computable parts. */=0A= =0A= static INLINE void=0A= init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)=0A= {=0A= const CGEN_INSN *insn_table =3D CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))-= >init_entries;=0A= =0A= id->num =3D t->index;=0A= id->sfmt =3D t->sfmt;=0A= if ((int) t->type <=3D 0)=0A= id->idata =3D & cgen_virtual_insn_table[- (int) t->type];=0A= else=0A= id->idata =3D & insn_table[t->type];=0A= id->attrs =3D CGEN_INSN_ATTRS (id->idata);=0A= /* Oh my god, a magic number. */=0A= id->length =3D CGEN_INSN_BITSIZE (id->idata) / 8;=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= id->timing =3D & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];=0A= {=0A= SIM_DESC sd =3D CPU_STATE (cpu);=0A= SIM_ASSERT (t->index =3D=3D id->timing->num);=0A= }=0A= #endif=0A= =0A= /* Semantic pointers are initialized elsewhere. */=0A= }=0A= =0A= /* Initialize the instruction descriptor table. */=0A= =0A= void=0A= m32r2f_init_idesc_table (SIM_CPU *cpu)=0A= {=0A= IDESC *id,*tabend;=0A= const struct insn_sem *t,*tend;=0A= int tabsize =3D M32R2F_INSN__MAX;=0A= IDESC *table =3D m32r2f_insn_data;=0A= =0A= memset (table, 0, tabsize * sizeof (IDESC));=0A= =0A= /* First set all entries to the `invalid insn'. */=0A= t =3D & m32r2f_insn_sem_invalid;=0A= for (id =3D table, tabend =3D table + tabsize; id < tabend; ++id)=0A= init_idesc (cpu, id, t);=0A= =0A= /* Now fill in the values for the chosen cpu. */=0A= for (t =3D m32r2f_insn_sem, tend =3D t + sizeof (m32r2f_insn_sem) / sizeo= f (*t);=0A= t !=3D tend; ++t)=0A= {=0A= init_idesc (cpu, & table[t->index], t);=0A= if (t->par_index !=3D NOPAR)=0A= {=0A= init_idesc (cpu, &table[t->par_index], t);=0A= table[t->index].par_idesc =3D &table[t->par_index];=0A= }=0A= if (t->par_index !=3D NOPAR)=0A= {=0A= init_idesc (cpu, &table[t->write_index], t);=0A= table[t->par_index].par_idesc =3D &table[t->write_index];=0A= }=0A= }=0A= =0A= /* Link the IDESC table into the cpu. */=0A= CPU_IDESC (cpu) =3D table;=0A= }=0A= =0A= /* Given an instruction, return a pointer to its IDESC entry. */=0A= =0A= const IDESC *=0A= m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,=0A= CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,=0A= ARGBUF *abuf)=0A= {=0A= /* Result of decoder. */=0A= M32R2F_INSN_TYPE itype;=0A= =0A= {=0A= CGEN_INSN_INT insn =3D base_insn;=0A= =0A= {=0A= unsigned int val =3D (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 = << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_SUBV; goto extract_sfmt_addv;=0A= case 1 : itype =3D M32R2F_INSN_SUBX; goto extract_sfmt_addx;=0A= case 2 : itype =3D M32R2F_INSN_SUB; goto extract_sfmt_add;=0A= case 3 : itype =3D M32R2F_INSN_NEG; goto extract_sfmt_mv;=0A= case 4 : itype =3D M32R2F_INSN_CMP; goto extract_sfmt_cmp;=0A= case 5 : itype =3D M32R2F_INSN_CMPU; goto extract_sfmt_cmp;=0A= case 6 : itype =3D M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp;=0A= case 7 :=0A= {=0A= unsigned int val =3D (((insn >> 8) & (3 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_CMPZ; goto extract_sfmt_cmpz;=0A= case 3 : itype =3D M32R2F_INSN_PCMPBZ; goto extract_sfmt_cmpz;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 8 : itype =3D M32R2F_INSN_ADDV; goto extract_sfmt_addv;=0A= case 9 : itype =3D M32R2F_INSN_ADDX; goto extract_sfmt_addx;=0A= case 10 : itype =3D M32R2F_INSN_ADD; goto extract_sfmt_add;=0A= case 11 : itype =3D M32R2F_INSN_NOT; goto extract_sfmt_mv;=0A= case 12 : itype =3D M32R2F_INSN_AND; goto extract_sfmt_add;=0A= case 13 : itype =3D M32R2F_INSN_XOR; goto extract_sfmt_add;=0A= case 14 : itype =3D M32R2F_INSN_OR; goto extract_sfmt_add;=0A= case 15 : itype =3D M32R2F_INSN_BTST; goto extract_sfmt_btst;=0A= case 16 : itype =3D M32R2F_INSN_SRL; goto extract_sfmt_add;=0A= case 18 : itype =3D M32R2F_INSN_SRA; goto extract_sfmt_add;=0A= case 20 : itype =3D M32R2F_INSN_SLL; goto extract_sfmt_add;=0A= case 22 : itype =3D M32R2F_INSN_MUL; goto extract_sfmt_add;=0A= case 24 : itype =3D M32R2F_INSN_MV; goto extract_sfmt_mv;=0A= case 25 : itype =3D M32R2F_INSN_MVFC; goto extract_sfmt_mvfc;=0A= case 26 : itype =3D M32R2F_INSN_MVTC; goto extract_sfmt_mvtc;=0A= case 28 :=0A= {=0A= unsigned int val =3D (((insn >> 8) & (3 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_JC; goto extract_sfmt_jc;=0A= case 1 : itype =3D M32R2F_INSN_JNC; goto extract_sfmt_jc;=0A= case 2 : itype =3D M32R2F_INSN_JL; goto extract_sfmt_jl;=0A= case 3 : itype =3D M32R2F_INSN_JMP; goto extract_sfmt_jmp;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 29 : itype =3D M32R2F_INSN_RTE; goto extract_sfmt_rte;=0A= case 31 : itype =3D M32R2F_INSN_TRAP; goto extract_sfmt_trap;=0A= case 32 : itype =3D M32R2F_INSN_STB; goto extract_sfmt_stb;=0A= case 33 : itype =3D M32R2F_INSN_STB_PLUS; goto extract_sfmt_stb_plus;= =0A= case 34 : itype =3D M32R2F_INSN_STH; goto extract_sfmt_sth;=0A= case 35 : itype =3D M32R2F_INSN_STH_PLUS; goto extract_sfmt_sth_plus;= =0A= case 36 : itype =3D M32R2F_INSN_ST; goto extract_sfmt_st;=0A= case 37 : itype =3D M32R2F_INSN_UNLOCK; goto extract_sfmt_unlock;=0A= case 38 : itype =3D M32R2F_INSN_ST_PLUS; goto extract_sfmt_st_plus;= =0A= case 39 : itype =3D M32R2F_INSN_ST_MINUS; goto extract_sfmt_st_plus;= =0A= case 40 : itype =3D M32R2F_INSN_LDB; goto extract_sfmt_ldb;=0A= case 41 : itype =3D M32R2F_INSN_LDUB; goto extract_sfmt_ldb;=0A= case 42 : itype =3D M32R2F_INSN_LDH; goto extract_sfmt_ldh;=0A= case 43 : itype =3D M32R2F_INSN_LDUH; goto extract_sfmt_ldh;=0A= case 44 : itype =3D M32R2F_INSN_LD; goto extract_sfmt_ld;=0A= case 45 : itype =3D M32R2F_INSN_LOCK; goto extract_sfmt_lock;=0A= case 46 : itype =3D M32R2F_INSN_LD_PLUS; goto extract_sfmt_ld_plus;= =0A= case 48 : /* fall through */=0A= case 56 : itype =3D M32R2F_INSN_MULHI_A; goto extract_sfmt_mulhi_a;= =0A= case 49 : /* fall through */=0A= case 57 : itype =3D M32R2F_INSN_MULLO_A; goto extract_sfmt_mulhi_a;= =0A= case 50 : /* fall through */=0A= case 58 : itype =3D M32R2F_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;= =0A= case 51 : /* fall through */=0A= case 59 : itype =3D M32R2F_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;= =0A= case 52 : /* fall through */=0A= case 60 : itype =3D M32R2F_INSN_MACHI_A; goto extract_sfmt_machi_a;= =0A= case 53 : /* fall through */=0A= case 61 : itype =3D M32R2F_INSN_MACLO_A; goto extract_sfmt_machi_a;= =0A= case 54 : /* fall through */=0A= case 62 : itype =3D M32R2F_INSN_MACWHI_A; goto extract_sfmt_machi_a;= =0A= case 55 : /* fall through */=0A= case 63 : itype =3D M32R2F_INSN_MACWLO_A; goto extract_sfmt_machi_a;= =0A= case 64 : /* fall through */=0A= case 65 : /* fall through */=0A= case 66 : /* fall through */=0A= case 67 : /* fall through */=0A= case 68 : /* fall through */=0A= case 69 : /* fall through */=0A= case 70 : /* fall through */=0A= case 71 : /* fall through */=0A= case 72 : /* fall through */=0A= case 73 : /* fall through */=0A= case 74 : /* fall through */=0A= case 75 : /* fall through */=0A= case 76 : /* fall through */=0A= case 77 : /* fall through */=0A= case 78 : /* fall through */=0A= case 79 : itype =3D M32R2F_INSN_ADDI; goto extract_sfmt_addi;=0A= case 80 : /* fall through */=0A= case 81 : itype =3D M32R2F_INSN_SRLI; goto extract_sfmt_slli;=0A= case 82 : /* fall through */=0A= case 83 : itype =3D M32R2F_INSN_SRAI; goto extract_sfmt_slli;=0A= case 84 : /* fall through */=0A= case 85 : itype =3D M32R2F_INSN_SLLI; goto extract_sfmt_slli;=0A= case 87 :=0A= {=0A= unsigned int val =3D (((insn >> 0) & (1 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_MVTACHI_A; goto extract_sfmt_mvtac= hi_a;=0A= case 1 : itype =3D M32R2F_INSN_MVTACLO_A; goto extract_sfmt_mvtac= hi_a;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 88 : itype =3D M32R2F_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;= =0A= case 89 : itype =3D M32R2F_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;= =0A= case 90 : itype =3D M32R2F_INSN_MULWU1; goto extract_sfmt_mulwu1;=0A= case 91 : itype =3D M32R2F_INSN_MACWU1; goto extract_sfmt_macwu1;=0A= case 92 : itype =3D M32R2F_INSN_MACLH1; goto extract_sfmt_macwu1;=0A= case 93 : itype =3D M32R2F_INSN_MSBLO; goto extract_sfmt_msblo;=0A= case 94 : itype =3D M32R2F_INSN_SADD; goto extract_sfmt_sadd;=0A= case 95 :=0A= {=0A= unsigned int val =3D (((insn >> 0) & (3 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfac= hi_a;=0A= case 1 : itype =3D M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfac= hi_a;=0A= case 2 : itype =3D M32R2F_INSN_MVFACMI_A; goto extract_sfmt_mvfac= hi_a;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 96 : /* fall through */=0A= case 97 : /* fall through */=0A= case 98 : /* fall through */=0A= case 99 : /* fall through */=0A= case 100 : /* fall through */=0A= case 101 : /* fall through */=0A= case 102 : /* fall through */=0A= case 103 : /* fall through */=0A= case 104 : /* fall through */=0A= case 105 : /* fall through */=0A= case 106 : /* fall through */=0A= case 107 : /* fall through */=0A= case 108 : /* fall through */=0A= case 109 : /* fall through */=0A= case 110 : /* fall through */=0A= case 111 : itype =3D M32R2F_INSN_LDI8; goto extract_sfmt_ldi8;=0A= case 112 :=0A= {=0A= unsigned int val =3D (((insn >> 7) & (15 << 1)) | ((insn >> 0) & = (1 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_NOP; goto extract_sfmt_nop;=0A= case 2 : /* fall through */=0A= case 3 : itype =3D M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;= =0A= case 4 : /* fall through */=0A= case 5 : itype =3D M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;= =0A= case 9 : itype =3D M32R2F_INSN_SC; goto extract_sfmt_sc;=0A= case 11 : itype =3D M32R2F_INSN_SNC; goto extract_sfmt_sc;=0A= case 16 : /* fall through */=0A= case 17 : itype =3D M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;=0A= case 18 : /* fall through */=0A= case 19 : itype =3D M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;=0A= case 24 : /* fall through */=0A= case 25 : itype =3D M32R2F_INSN_BC8; goto extract_sfmt_bc8;=0A= case 26 : /* fall through */=0A= case 27 : itype =3D M32R2F_INSN_BNC8; goto extract_sfmt_bc8;=0A= case 28 : /* fall through */=0A= case 29 : itype =3D M32R2F_INSN_BL8; goto extract_sfmt_bl8;=0A= case 30 : /* fall through */=0A= case 31 : itype =3D M32R2F_INSN_BRA8; goto extract_sfmt_bra8;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 113 : /* fall through */=0A= case 114 : /* fall through */=0A= case 115 : /* fall through */=0A= case 116 : /* fall through */=0A= case 117 : /* fall through */=0A= case 118 : /* fall through */=0A= case 119 : /* fall through */=0A= case 120 : /* fall through */=0A= case 121 : /* fall through */=0A= case 122 : /* fall through */=0A= case 123 : /* fall through */=0A= case 124 : /* fall through */=0A= case 125 : /* fall through */=0A= case 126 : /* fall through */=0A= case 127 :=0A= {=0A= unsigned int val =3D (((insn >> 8) & (15 << 0)));=0A= switch (val)=0A= {=0A= case 1 : itype =3D M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;= =0A= case 2 : itype =3D M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;= =0A= case 8 : itype =3D M32R2F_INSN_BCL8; goto extract_sfmt_bcl8;=0A= case 9 : itype =3D M32R2F_INSN_BNCL8; goto extract_sfmt_bcl8;=0A= case 12 : itype =3D M32R2F_INSN_BC8; goto extract_sfmt_bc8;=0A= case 13 : itype =3D M32R2F_INSN_BNC8; goto extract_sfmt_bc8;=0A= case 14 : itype =3D M32R2F_INSN_BL8; goto extract_sfmt_bl8;=0A= case 15 : itype =3D M32R2F_INSN_BRA8; goto extract_sfmt_bra8;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 132 : itype =3D M32R2F_INSN_CMPI; goto extract_sfmt_cmpi;=0A= case 133 : itype =3D M32R2F_INSN_CMPUI; goto extract_sfmt_cmpi;=0A= case 134 :=0A= {=0A= unsigned int val =3D (((insn >> -8) & (3 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_SAT; goto extract_sfmt_sat;=0A= case 2 : itype =3D M32R2F_INSN_SATH; goto extract_sfmt_satb;=0A= case 3 : itype =3D M32R2F_INSN_SATB; goto extract_sfmt_satb;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 136 : itype =3D M32R2F_INSN_ADDV3; goto extract_sfmt_addv3;=0A= case 138 : itype =3D M32R2F_INSN_ADD3; goto extract_sfmt_add3;=0A= case 140 : itype =3D M32R2F_INSN_AND3; goto extract_sfmt_and3;=0A= case 141 : itype =3D M32R2F_INSN_XOR3; goto extract_sfmt_and3;=0A= case 142 : itype =3D M32R2F_INSN_OR3; goto extract_sfmt_or3;=0A= case 144 :=0A= {=0A= unsigned int val =3D (((insn >> -13) & (3 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_DIV; goto extract_sfmt_div;=0A= case 2 : itype =3D M32R2F_INSN_DIVH; goto extract_sfmt_div;=0A= case 3 : itype =3D M32R2F_INSN_DIVB; goto extract_sfmt_div;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 145 :=0A= {=0A= unsigned int val =3D (((insn >> -13) & (3 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_DIVU; goto extract_sfmt_div;=0A= case 2 : itype =3D M32R2F_INSN_DIVUH; goto extract_sfmt_div;=0A= case 3 : itype =3D M32R2F_INSN_DIVUB; goto extract_sfmt_div;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 146 :=0A= {=0A= unsigned int val =3D (((insn >> -13) & (3 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_REM; goto extract_sfmt_div;=0A= case 2 : itype =3D M32R2F_INSN_REMH; goto extract_sfmt_div;=0A= case 3 : itype =3D M32R2F_INSN_REMB; goto extract_sfmt_div;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 147 :=0A= {=0A= unsigned int val =3D (((insn >> -13) & (3 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_REMU; goto extract_sfmt_div;=0A= case 2 : itype =3D M32R2F_INSN_REMUH; goto extract_sfmt_div;=0A= case 3 : itype =3D M32R2F_INSN_REMUB; goto extract_sfmt_div;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= case 152 : itype =3D M32R2F_INSN_SRL3; goto extract_sfmt_sll3;=0A= case 154 : itype =3D M32R2F_INSN_SRA3; goto extract_sfmt_sll3;=0A= case 156 : itype =3D M32R2F_INSN_SLL3; goto extract_sfmt_sll3;=0A= case 159 : itype =3D M32R2F_INSN_LDI16; goto extract_sfmt_ldi16;=0A= case 160 : itype =3D M32R2F_INSN_STB_D; goto extract_sfmt_stb_d;=0A= case 162 : itype =3D M32R2F_INSN_STH_D; goto extract_sfmt_sth_d;=0A= case 164 : itype =3D M32R2F_INSN_ST_D; goto extract_sfmt_st_d;=0A= case 166 : itype =3D M32R2F_INSN_BSET; goto extract_sfmt_bset;=0A= case 167 : itype =3D M32R2F_INSN_BCLR; goto extract_sfmt_bset;=0A= case 168 : itype =3D M32R2F_INSN_LDB_D; goto extract_sfmt_ldb_d;=0A= case 169 : itype =3D M32R2F_INSN_LDUB_D; goto extract_sfmt_ldb_d;=0A= case 170 : itype =3D M32R2F_INSN_LDH_D; goto extract_sfmt_ldh_d;=0A= case 171 : itype =3D M32R2F_INSN_LDUH_D; goto extract_sfmt_ldh_d;=0A= case 172 : itype =3D M32R2F_INSN_LD_D; goto extract_sfmt_ld_d;=0A= case 176 : itype =3D M32R2F_INSN_BEQ; goto extract_sfmt_beq;=0A= case 177 : itype =3D M32R2F_INSN_BNE; goto extract_sfmt_beq;=0A= case 184 : itype =3D M32R2F_INSN_BEQZ; goto extract_sfmt_beqz;=0A= case 185 : itype =3D M32R2F_INSN_BNEZ; goto extract_sfmt_beqz;=0A= case 186 : itype =3D M32R2F_INSN_BLTZ; goto extract_sfmt_beqz;=0A= case 187 : itype =3D M32R2F_INSN_BGEZ; goto extract_sfmt_beqz;=0A= case 188 : itype =3D M32R2F_INSN_BLEZ; goto extract_sfmt_beqz;=0A= case 189 : itype =3D M32R2F_INSN_BGTZ; goto extract_sfmt_beqz;=0A= case 220 : itype =3D M32R2F_INSN_SETH; goto extract_sfmt_seth;=0A= case 224 : /* fall through */=0A= case 225 : /* fall through */=0A= case 226 : /* fall through */=0A= case 227 : /* fall through */=0A= case 228 : /* fall through */=0A= case 229 : /* fall through */=0A= case 230 : /* fall through */=0A= case 231 : /* fall through */=0A= case 232 : /* fall through */=0A= case 233 : /* fall through */=0A= case 234 : /* fall through */=0A= case 235 : /* fall through */=0A= case 236 : /* fall through */=0A= case 237 : /* fall through */=0A= case 238 : /* fall through */=0A= case 239 : itype =3D M32R2F_INSN_LD24; goto extract_sfmt_ld24;=0A= case 240 : /* fall through */=0A= case 241 : /* fall through */=0A= case 242 : /* fall through */=0A= case 243 : /* fall through */=0A= case 244 : /* fall through */=0A= case 245 : /* fall through */=0A= case 246 : /* fall through */=0A= case 247 : /* fall through */=0A= case 248 : /* fall through */=0A= case 249 : /* fall through */=0A= case 250 : /* fall through */=0A= case 251 : /* fall through */=0A= case 252 : /* fall through */=0A= case 253 : /* fall through */=0A= case 254 : /* fall through */=0A= case 255 :=0A= {=0A= unsigned int val =3D (((insn >> 8) & (7 << 0)));=0A= switch (val)=0A= {=0A= case 0 : itype =3D M32R2F_INSN_BCL24; goto extract_sfmt_bcl24;=0A= case 1 : itype =3D M32R2F_INSN_BNCL24; goto extract_sfmt_bcl24;= =0A= case 4 : itype =3D M32R2F_INSN_BC24; goto extract_sfmt_bc24;=0A= case 5 : itype =3D M32R2F_INSN_BNC24; goto extract_sfmt_bc24;=0A= case 6 : itype =3D M32R2F_INSN_BL24; goto extract_sfmt_bl24;=0A= case 7 : itype =3D M32R2F_INSN_BRA24; goto extract_sfmt_bra24;=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empt= y;=0A= }=0A= }=0A= default : itype =3D M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;= =0A= }=0A= }=0A= }=0A= =0A= /* The instruction has been decoded, now extract the fields. */=0A= =0A= extract_sfmt_empty:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= =0A= =0A= /* Record the fields for the semantic handler. */=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *= ) 0));=0A= =0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_add:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%= x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x'= , f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_dr) =3D f_r1;=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_add3:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm1= 6 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr= 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_and3:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_and3.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= UINT f_uimm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_uimm16 =3D EXTRACT_MSB0_UINT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_uimm16) =3D f_uimm16;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x= %x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr= 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_or3:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_and3.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= UINT f_uimm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_uimm16 =3D EXTRACT_MSB0_UINT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_uimm16) =3D f_uimm16;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%= x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr = 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_addi:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= UINT f_r1;=0A= INT f_simm8;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_simm8 =3D EXTRACT_MSB0_INT (insn, 16, 8, 8);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_simm8) =3D f_simm8;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x= %x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *= ) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_dr) =3D f_r1;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_addv:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x= %x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x= ', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_dr) =3D f_r1;=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_addv3:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm= 16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "s= r 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_addx:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x= %x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x= ', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_dr) =3D f_r1;=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bc8:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= SI f_disp8;=0A= =0A= f_disp8 =3D ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & = (-4))));=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (i_disp8) =3D f_disp8;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x= %x", 'x', f_disp8, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bc24:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= SI f_disp24;=0A= =0A= f_disp24 =3D ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));= =0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (i_disp24) =3D f_disp24;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 = 0x%x", 'x', f_disp24, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_beq:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= SI f_disp16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_disp16 =3D ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));= =0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_disp16) =3D f_disp16;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%= x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 = 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_beqz:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_beq.f=0A= UINT f_r2;=0A= SI f_disp16;=0A= =0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_disp16 =3D ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));= =0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_disp16) =3D f_disp16;=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x= %x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char= *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bl8:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= SI f_disp8;=0A= =0A= f_disp8 =3D ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & = (-4))));=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (i_disp8) =3D f_disp8;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x= %x", 'x', f_disp8, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_h_gr_SI_14) =3D 14;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bl24:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= SI f_disp24;=0A= =0A= f_disp24 =3D ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));= =0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (i_disp24) =3D f_disp24;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 = 0x%x", 'x', f_disp24, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_h_gr_SI_14) =3D 14;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bcl8:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= SI f_disp8;=0A= =0A= f_disp8 =3D ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & = (-4))));=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (i_disp8) =3D f_disp8;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0= x%x", 'x', f_disp8, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_h_gr_SI_14) =3D 14;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bcl24:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= SI f_disp24;=0A= =0A= f_disp24 =3D ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));= =0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (i_disp24) =3D f_disp24;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24= 0x%x", 'x', f_disp24, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_h_gr_SI_14) =3D 14;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bra8:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bl8.f=0A= SI f_disp8;=0A= =0A= f_disp8 =3D ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & = (-4))));=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (i_disp8) =3D f_disp8;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0= x%x", 'x', f_disp8, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bra24:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bl24.f=0A= SI f_disp24;=0A= =0A= f_disp24 =3D ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));= =0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (i_disp24) =3D f_disp24;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24= 0x%x", 'x', f_disp24, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_cmp:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%= x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x",= 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_cmpi:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm1= 6 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (ch= ar *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_cmpz:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r2;=0A= =0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x= %x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_div:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%= x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x'= , f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_dr) =3D f_r1;=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_jc:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= UINT f_r2;=0A= =0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x= ", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_jl:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= UINT f_r2;=0A= =0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x= ", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_h_gr_SI_14) =3D 14;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_jmp:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_jl.f=0A= UINT f_r2;=0A= =0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%= x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ld:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x= ", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x',= f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ld_d:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm1= 6 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr= 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ldb:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%= x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x'= , f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ldb_d:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm= 16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "s= r 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ldh:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%= x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x'= , f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ldh_d:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm= 16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "s= r 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ld_plus:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2= 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x",= 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= FLD (out_sr) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ld24:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld24.f=0A= UINT f_r1;=0A= UINT f_uimm24;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_uimm24 =3D EXTRACT_MSB0_UINT (insn, 32, 8, 24);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_uimm24) =3D f_uimm24;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x= %x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *= ) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ldi8:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_addi.f=0A= UINT f_r1;=0A= INT f_simm8;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_simm8 =3D EXTRACT_MSB0_INT (insn, 16, 8, 8);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm8) =3D f_simm8;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8= 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *= ) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_ldi16:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= UINT f_r1;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm= 16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (cha= r *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_lock:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x= %x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x= ', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_machi_a:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= UINT f_r1;=0A= UINT f_acc;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_acc =3D EXTRACT_MSB0_UINT (insn, 16, 8, 1);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_acc) =3D f_acc;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_ac= c 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 = 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_mulhi_a:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_machi_a.f=0A= UINT f_r1;=0A= UINT f_acc;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_acc =3D EXTRACT_MSB0_UINT (insn, 16, 8, 1);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_acc) =3D f_acc;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1= 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 = 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_mv:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x= ", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x',= f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_mvfachi_a:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_mvfachi_a.f=0A= UINT f_r1;=0A= UINT f_accs;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_accs =3D EXTRACT_MSB0_UINT (insn, 16, 12, 2);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_accs) =3D f_accs;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_= accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (cha= r *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_mvfc:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x= %x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));= =0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_mvtachi_a:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_mvtachi_a.f=0A= UINT f_r1;=0A= UINT f_accs;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_accs =3D EXTRACT_MSB0_UINT (insn, 16, 12, 2);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_accs) =3D f_accs;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_= accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (c= har *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_mvtc:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x= %x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));= =0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_nop:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= =0A= =0A= /* Record the fields for the semantic handler. */=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) = 0));=0A= =0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_rac_dsi:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_rac_dsi.f=0A= UINT f_accd;=0A= UINT f_accs;=0A= SI f_imm1;=0A= =0A= f_accd =3D EXTRACT_MSB0_UINT (insn, 16, 4, 2);=0A= f_accs =3D EXTRACT_MSB0_UINT (insn, 16, 12, 2);=0A= f_imm1 =3D ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_accs) =3D f_accs;=0A= FLD (f_imm1) =3D f_imm1;=0A= FLD (f_accd) =3D f_accd;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_ac= cs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_ac= cd, (char *) 0));=0A= =0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_rte:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= =0A= =0A= /* Record the fields for the semantic handler. */=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) = 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_seth:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_seth.f=0A= UINT f_r1;=0A= UINT f_hi16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_hi16 =3D EXTRACT_MSB0_UINT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_hi16) =3D f_hi16;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 = 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) = 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_sll3:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_add3.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm1= 6 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr= 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_slli:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_slli.f=0A= UINT f_r1;=0A= UINT f_uimm5;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_uimm5 =3D EXTRACT_MSB0_UINT (insn, 16, 11, 5);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_uimm5) =3D f_uimm5;=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x= %x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *= ) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_dr) =3D f_r1;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_st:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x= ", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", = 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_st_d:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm1= 6 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "sr= c1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_stb:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%= x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x",= 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_stb_d:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm= 16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "s= rc1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_sth:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%= x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x",= 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_sth_d:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_d.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm= 16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "s= rc1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_st_plus:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1= 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x= %x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= FLD (out_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_sth_plus:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r= 1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0= x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= FLD (out_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_stb_plus:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r= 1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0= x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= FLD (out_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_trap:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_trap.f=0A= UINT f_uimm4;=0A= =0A= f_uimm4 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_uimm4) =3D f_uimm4;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4= 0x%x", 'x', f_uimm4, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_unlock:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 = 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%= x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_satb:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x= %x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x= ', f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_sat:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_ld_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 32, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_r1) =3D f_r1;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= FLD (i_dr) =3D & CPU (h_gr)[f_r1];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%= x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x'= , f_r1, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= FLD (out_dr) =3D f_r1;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_sadd:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= =0A= =0A= /* Record the fields for the semantic handler. */=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *)= 0));=0A= =0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_macwu1:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 = 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%= x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_msblo:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0= x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x= ", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_mulwu1:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_st_plus.f=0A= UINT f_r1;=0A= UINT f_r2;=0A= =0A= f_r1 =3D EXTRACT_MSB0_UINT (insn, 16, 4, 4);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r1) =3D f_r1;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (i_src1) =3D & CPU (h_gr)[f_r1];=0A= FLD (i_src2) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 = 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%= x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_src1) =3D f_r1;=0A= FLD (in_src2) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_sc:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= #define FLD(f) abuf->fields.fmt_empty.f=0A= =0A= =0A= /* Record the fields for the semantic handler. */=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0= ));=0A= =0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_clrpsw:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= UINT f_uimm8;=0A= =0A= f_uimm8 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 8);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_uimm8) =3D f_uimm8;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uim= m8 0x%x", 'x', f_uimm8, (char *) 0));=0A= =0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_setpsw:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_clrpsw.f=0A= UINT f_uimm8;=0A= =0A= f_uimm8 =3D EXTRACT_MSB0_UINT (insn, 16, 8, 8);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_uimm8) =3D f_uimm8;=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uim= m8 0x%x", 'x', f_uimm8, (char *) 0));=0A= =0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_bset:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= UINT f_uimm3;=0A= UINT f_r2;=0A= INT f_simm16;=0A= =0A= f_uimm3 =3D EXTRACT_MSB0_UINT (insn, 32, 5, 3);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 32, 12, 4);=0A= f_simm16 =3D EXTRACT_MSB0_INT (insn, 32, 16, 16);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_simm16) =3D f_simm16;=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_uimm3) =3D f_uimm3;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm1= 6 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm= 3, "sr 0x%x", 'x', f_r2, (char *) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= extract_sfmt_btst:=0A= {=0A= const IDESC *idesc =3D &m32r2f_insn_data[itype];=0A= CGEN_INSN_INT insn =3D entire_insn;=0A= #define FLD(f) abuf->fields.sfmt_bset.f=0A= UINT f_uimm3;=0A= UINT f_r2;=0A= =0A= f_uimm3 =3D EXTRACT_MSB0_UINT (insn, 16, 5, 3);=0A= f_r2 =3D EXTRACT_MSB0_UINT (insn, 16, 12, 4);=0A= =0A= /* Record the fields for the semantic handler. */=0A= FLD (f_r2) =3D f_r2;=0A= FLD (f_uimm3) =3D f_uimm3;=0A= FLD (i_sr) =3D & CPU (h_gr)[f_r2];=0A= TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x= %x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *= ) 0));=0A= =0A= #if WITH_PROFILE_MODEL_P=0A= /* Record the fields for profiling. */=0A= if (PROFILE_MODEL_P (current_cpu))=0A= {=0A= FLD (in_sr) =3D f_r2;=0A= }=0A= #endif=0A= #undef FLD=0A= return idesc;=0A= }=0A= =0A= }=0A= --Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ) Content-type: application/octet-stream; name=decode2.h Content-transfer-encoding: quoted-printable Content-disposition: attachment; filename=decode2.h Content-length: 11271 /* Decode header for m32r2f.=0A= =0A= THIS FILE IS MACHINE GENERATED WITH CGEN.=0A= =0A= Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foun= dation, Inc.=0A= =0A= This file is part of the GNU simulators.=0A= =0A= This program is free software; you can redistribute it and/or modify=0A= it under the terms of the GNU General Public License as published by=0A= the Free Software Foundation; either version 2, or (at your option)=0A= any later version.=0A= =0A= This program is distributed in the hope that it will be useful,=0A= but WITHOUT ANY WARRANTY; without even the implied warranty of=0A= MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the=0A= GNU General Public License for more details.=0A= =0A= You should have received a copy of the GNU General Public License along=0A= with this program; if not, write to the Free Software Foundation, Inc.,=0A= 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.=0A= =0A= */=0A= =0A= #ifndef M32R2F_DECODE_H=0A= #define M32R2F_DECODE_H=0A= =0A= extern const IDESC *m32r2f_decode (SIM_CPU *, IADDR,=0A= CGEN_INSN_INT, CGEN_INSN_INT,=0A= ARGBUF *);=0A= extern void m32r2f_init_idesc_table (SIM_CPU *);=0A= extern void m32r2f_sem_init_idesc_table (SIM_CPU *);=0A= extern void m32r2f_semf_init_idesc_table (SIM_CPU *);=0A= =0A= /* Enum declaration for instructions in cpu family m32r2f. */=0A= typedef enum m32r2f_insn_type {=0A= M32R2F_INSN_X_INVALID, M32R2F_INSN_X_AFTER, M32R2F_INSN_X_BEFORE, M32R2F_= INSN_X_CTI_CHAIN=0A= , M32R2F_INSN_X_CHAIN, M32R2F_INSN_X_BEGIN, M32R2F_INSN_ADD, M32R2F_INSN_A= DD3=0A= , M32R2F_INSN_AND, M32R2F_INSN_AND3, M32R2F_INSN_OR, M32R2F_INSN_OR3=0A= , M32R2F_INSN_XOR, M32R2F_INSN_XOR3, M32R2F_INSN_ADDI, M32R2F_INSN_ADDV=0A= , M32R2F_INSN_ADDV3, M32R2F_INSN_ADDX, M32R2F_INSN_BC8, M32R2F_INSN_BC24= =0A= , M32R2F_INSN_BEQ, M32R2F_INSN_BEQZ, M32R2F_INSN_BGEZ, M32R2F_INSN_BGTZ=0A= , M32R2F_INSN_BLEZ, M32R2F_INSN_BLTZ, M32R2F_INSN_BNEZ, M32R2F_INSN_BL8=0A= , M32R2F_INSN_BL24, M32R2F_INSN_BCL8, M32R2F_INSN_BCL24, M32R2F_INSN_BNC8= =0A= , M32R2F_INSN_BNC24, M32R2F_INSN_BNE, M32R2F_INSN_BRA8, M32R2F_INSN_BRA24= =0A= , M32R2F_INSN_BNCL8, M32R2F_INSN_BNCL24, M32R2F_INSN_CMP, M32R2F_INSN_CMPI= =0A= , M32R2F_INSN_CMPU, M32R2F_INSN_CMPUI, M32R2F_INSN_CMPEQ, M32R2F_INSN_CMPZ= =0A= , M32R2F_INSN_DIV, M32R2F_INSN_DIVU, M32R2F_INSN_REM, M32R2F_INSN_REMU=0A= , M32R2F_INSN_REMH, M32R2F_INSN_REMUH, M32R2F_INSN_REMB, M32R2F_INSN_REMUB= =0A= , M32R2F_INSN_DIVUH, M32R2F_INSN_DIVB, M32R2F_INSN_DIVUB, M32R2F_INSN_DIVH= =0A= , M32R2F_INSN_JC, M32R2F_INSN_JNC, M32R2F_INSN_JL, M32R2F_INSN_JMP=0A= , M32R2F_INSN_LD, M32R2F_INSN_LD_D, M32R2F_INSN_LDB, M32R2F_INSN_LDB_D=0A= , M32R2F_INSN_LDH, M32R2F_INSN_LDH_D, M32R2F_INSN_LDUB, M32R2F_INSN_LDUB_D= =0A= , M32R2F_INSN_LDUH, M32R2F_INSN_LDUH_D, M32R2F_INSN_LD_PLUS, M32R2F_INSN_L= D24=0A= , M32R2F_INSN_LDI8, M32R2F_INSN_LDI16, M32R2F_INSN_LOCK, M32R2F_INSN_MACHI= _A=0A= , M32R2F_INSN_MACLO_A, M32R2F_INSN_MACWHI_A, M32R2F_INSN_MACWLO_A, M32R2F_= INSN_MUL=0A= , M32R2F_INSN_MULHI_A, M32R2F_INSN_MULLO_A, M32R2F_INSN_MULWHI_A, M32R2F_I= NSN_MULWLO_A=0A= , M32R2F_INSN_MV, M32R2F_INSN_MVFACHI_A, M32R2F_INSN_MVFACLO_A, M32R2F_INS= N_MVFACMI_A=0A= , M32R2F_INSN_MVFC, M32R2F_INSN_MVTACHI_A, M32R2F_INSN_MVTACLO_A, M32R2F_I= NSN_MVTC=0A= , M32R2F_INSN_NEG, M32R2F_INSN_NOP, M32R2F_INSN_NOT, M32R2F_INSN_RAC_DSI= =0A= , M32R2F_INSN_RACH_DSI, M32R2F_INSN_RTE, M32R2F_INSN_SETH, M32R2F_INSN_SLL= =0A= , M32R2F_INSN_SLL3, M32R2F_INSN_SLLI, M32R2F_INSN_SRA, M32R2F_INSN_SRA3=0A= , M32R2F_INSN_SRAI, M32R2F_INSN_SRL, M32R2F_INSN_SRL3, M32R2F_INSN_SRLI=0A= , M32R2F_INSN_ST, M32R2F_INSN_ST_D, M32R2F_INSN_STB, M32R2F_INSN_STB_D=0A= , M32R2F_INSN_STH, M32R2F_INSN_STH_D, M32R2F_INSN_ST_PLUS, M32R2F_INSN_STH= _PLUS=0A= , M32R2F_INSN_STB_PLUS, M32R2F_INSN_ST_MINUS, M32R2F_INSN_SUB, M32R2F_INSN= _SUBV=0A= , M32R2F_INSN_SUBX, M32R2F_INSN_TRAP, M32R2F_INSN_UNLOCK, M32R2F_INSN_SATB= =0A= , M32R2F_INSN_SATH, M32R2F_INSN_SAT, M32R2F_INSN_PCMPBZ, M32R2F_INSN_SADD= =0A= , M32R2F_INSN_MACWU1, M32R2F_INSN_MSBLO, M32R2F_INSN_MULWU1, M32R2F_INSN_M= ACLH1=0A= , M32R2F_INSN_SC, M32R2F_INSN_SNC, M32R2F_INSN_CLRPSW, M32R2F_INSN_SETPSW= =0A= , M32R2F_INSN_BSET, M32R2F_INSN_BCLR, M32R2F_INSN_BTST, M32R2F_INSN_PAR_AD= D=0A= , M32R2F_INSN_WRITE_ADD, M32R2F_INSN_PAR_AND, M32R2F_INSN_WRITE_AND, M32R2= F_INSN_PAR_OR=0A= , M32R2F_INSN_WRITE_OR, M32R2F_INSN_PAR_XOR, M32R2F_INSN_WRITE_XOR, M32R2F= _INSN_PAR_ADDI=0A= , M32R2F_INSN_WRITE_ADDI, M32R2F_INSN_PAR_ADDV, M32R2F_INSN_WRITE_ADDV, M3= 2R2F_INSN_PAR_ADDX=0A= , M32R2F_INSN_WRITE_ADDX, M32R2F_INSN_PAR_BC8, M32R2F_INSN_WRITE_BC8, M32R= 2F_INSN_PAR_BL8=0A= , M32R2F_INSN_WRITE_BL8, M32R2F_INSN_PAR_BCL8, M32R2F_INSN_WRITE_BCL8, M32= R2F_INSN_PAR_BNC8=0A= , M32R2F_INSN_WRITE_BNC8, M32R2F_INSN_PAR_BRA8, M32R2F_INSN_WRITE_BRA8, M3= 2R2F_INSN_PAR_BNCL8=0A= , M32R2F_INSN_WRITE_BNCL8, M32R2F_INSN_PAR_CMP, M32R2F_INSN_WRITE_CMP, M32= R2F_INSN_PAR_CMPU=0A= , M32R2F_INSN_WRITE_CMPU, M32R2F_INSN_PAR_CMPEQ, M32R2F_INSN_WRITE_CMPEQ, = M32R2F_INSN_PAR_CMPZ=0A= , M32R2F_INSN_WRITE_CMPZ, M32R2F_INSN_PAR_JC, M32R2F_INSN_WRITE_JC, M32R2F= _INSN_PAR_JNC=0A= , M32R2F_INSN_WRITE_JNC, M32R2F_INSN_PAR_JL, M32R2F_INSN_WRITE_JL, M32R2F_= INSN_PAR_JMP=0A= , M32R2F_INSN_WRITE_JMP, M32R2F_INSN_PAR_LD, M32R2F_INSN_WRITE_LD, M32R2F_= INSN_PAR_LDB=0A= , M32R2F_INSN_WRITE_LDB, M32R2F_INSN_PAR_LDH, M32R2F_INSN_WRITE_LDH, M32R2= F_INSN_PAR_LDUB=0A= , M32R2F_INSN_WRITE_LDUB, M32R2F_INSN_PAR_LDUH, M32R2F_INSN_WRITE_LDUH, M3= 2R2F_INSN_PAR_LD_PLUS=0A= , M32R2F_INSN_WRITE_LD_PLUS, M32R2F_INSN_PAR_LDI8, M32R2F_INSN_WRITE_LDI8,= M32R2F_INSN_PAR_LOCK=0A= , M32R2F_INSN_WRITE_LOCK, M32R2F_INSN_PAR_MACHI_A, M32R2F_INSN_WRITE_MACHI= _A, M32R2F_INSN_PAR_MACLO_A=0A= , M32R2F_INSN_WRITE_MACLO_A, M32R2F_INSN_PAR_MACWHI_A, M32R2F_INSN_WRITE_M= ACWHI_A, M32R2F_INSN_PAR_MACWLO_A=0A= , M32R2F_INSN_WRITE_MACWLO_A, M32R2F_INSN_PAR_MUL, M32R2F_INSN_WRITE_MUL, = M32R2F_INSN_PAR_MULHI_A=0A= , M32R2F_INSN_WRITE_MULHI_A, M32R2F_INSN_PAR_MULLO_A, M32R2F_INSN_WRITE_MU= LLO_A, M32R2F_INSN_PAR_MULWHI_A=0A= , M32R2F_INSN_WRITE_MULWHI_A, M32R2F_INSN_PAR_MULWLO_A, M32R2F_INSN_WRITE_= MULWLO_A, M32R2F_INSN_PAR_MV=0A= , M32R2F_INSN_WRITE_MV, M32R2F_INSN_PAR_MVFACHI_A, M32R2F_INSN_WRITE_MVFAC= HI_A, M32R2F_INSN_PAR_MVFACLO_A=0A= , M32R2F_INSN_WRITE_MVFACLO_A, M32R2F_INSN_PAR_MVFACMI_A, M32R2F_INSN_WRIT= E_MVFACMI_A, M32R2F_INSN_PAR_MVFC=0A= , M32R2F_INSN_WRITE_MVFC, M32R2F_INSN_PAR_MVTACHI_A, M32R2F_INSN_WRITE_MVT= ACHI_A, M32R2F_INSN_PAR_MVTACLO_A=0A= , M32R2F_INSN_WRITE_MVTACLO_A, M32R2F_INSN_PAR_MVTC, M32R2F_INSN_WRITE_MVT= C, M32R2F_INSN_PAR_NEG=0A= , M32R2F_INSN_WRITE_NEG, M32R2F_INSN_PAR_NOP, M32R2F_INSN_WRITE_NOP, M32R2= F_INSN_PAR_NOT=0A= , M32R2F_INSN_WRITE_NOT, M32R2F_INSN_PAR_RAC_DSI, M32R2F_INSN_WRITE_RAC_DS= I, M32R2F_INSN_PAR_RACH_DSI=0A= , M32R2F_INSN_WRITE_RACH_DSI, M32R2F_INSN_PAR_RTE, M32R2F_INSN_WRITE_RTE, = M32R2F_INSN_PAR_SLL=0A= , M32R2F_INSN_WRITE_SLL, M32R2F_INSN_PAR_SLLI, M32R2F_INSN_WRITE_SLLI, M32= R2F_INSN_PAR_SRA=0A= , M32R2F_INSN_WRITE_SRA, M32R2F_INSN_PAR_SRAI, M32R2F_INSN_WRITE_SRAI, M32= R2F_INSN_PAR_SRL=0A= , M32R2F_INSN_WRITE_SRL, M32R2F_INSN_PAR_SRLI, M32R2F_INSN_WRITE_SRLI, M32= R2F_INSN_PAR_ST=0A= , M32R2F_INSN_WRITE_ST, M32R2F_INSN_PAR_STB, M32R2F_INSN_WRITE_STB, M32R2F= _INSN_PAR_STH=0A= , M32R2F_INSN_WRITE_STH, M32R2F_INSN_PAR_ST_PLUS, M32R2F_INSN_WRITE_ST_PLU= S, M32R2F_INSN_PAR_STH_PLUS=0A= , M32R2F_INSN_WRITE_STH_PLUS, M32R2F_INSN_PAR_STB_PLUS, M32R2F_INSN_WRITE_= STB_PLUS, M32R2F_INSN_PAR_ST_MINUS=0A= , M32R2F_INSN_WRITE_ST_MINUS, M32R2F_INSN_PAR_SUB, M32R2F_INSN_WRITE_SUB, = M32R2F_INSN_PAR_SUBV=0A= , M32R2F_INSN_WRITE_SUBV, M32R2F_INSN_PAR_SUBX, M32R2F_INSN_WRITE_SUBX, M3= 2R2F_INSN_PAR_TRAP=0A= , M32R2F_INSN_WRITE_TRAP, M32R2F_INSN_PAR_UNLOCK, M32R2F_INSN_WRITE_UNLOCK= , M32R2F_INSN_PAR_PCMPBZ=0A= , M32R2F_INSN_WRITE_PCMPBZ, M32R2F_INSN_PAR_SADD, M32R2F_INSN_WRITE_SADD, = M32R2F_INSN_PAR_MACWU1=0A= , M32R2F_INSN_WRITE_MACWU1, M32R2F_INSN_PAR_MSBLO, M32R2F_INSN_WRITE_MSBLO= , M32R2F_INSN_PAR_MULWU1=0A= , M32R2F_INSN_WRITE_MULWU1, M32R2F_INSN_PAR_MACLH1, M32R2F_INSN_WRITE_MACL= H1, M32R2F_INSN_PAR_SC=0A= , M32R2F_INSN_WRITE_SC, M32R2F_INSN_PAR_SNC, M32R2F_INSN_WRITE_SNC, M32R2F= _INSN_PAR_CLRPSW=0A= , M32R2F_INSN_WRITE_CLRPSW, M32R2F_INSN_PAR_SETPSW, M32R2F_INSN_WRITE_SETP= SW, M32R2F_INSN_PAR_BTST=0A= , M32R2F_INSN_WRITE_BTST, M32R2F_INSN__MAX=0A= } M32R2F_INSN_TYPE;=0A= =0A= /* Enum declaration for semantic formats in cpu family m32r2f. */=0A= typedef enum m32r2f_sfmt_type {=0A= M32R2F_SFMT_EMPTY, M32R2F_SFMT_ADD, M32R2F_SFMT_ADD3, M32R2F_SFMT_AND3=0A= , M32R2F_SFMT_OR3, M32R2F_SFMT_ADDI, M32R2F_SFMT_ADDV, M32R2F_SFMT_ADDV3= =0A= , M32R2F_SFMT_ADDX, M32R2F_SFMT_BC8, M32R2F_SFMT_BC24, M32R2F_SFMT_BEQ=0A= , M32R2F_SFMT_BEQZ, M32R2F_SFMT_BL8, M32R2F_SFMT_BL24, M32R2F_SFMT_BCL8=0A= , M32R2F_SFMT_BCL24, M32R2F_SFMT_BRA8, M32R2F_SFMT_BRA24, M32R2F_SFMT_CMP= =0A= , M32R2F_SFMT_CMPI, M32R2F_SFMT_CMPZ, M32R2F_SFMT_DIV, M32R2F_SFMT_JC=0A= , M32R2F_SFMT_JL, M32R2F_SFMT_JMP, M32R2F_SFMT_LD, M32R2F_SFMT_LD_D=0A= , M32R2F_SFMT_LDB, M32R2F_SFMT_LDB_D, M32R2F_SFMT_LDH, M32R2F_SFMT_LDH_D= =0A= , M32R2F_SFMT_LD_PLUS, M32R2F_SFMT_LD24, M32R2F_SFMT_LDI8, M32R2F_SFMT_LDI= 16=0A= , M32R2F_SFMT_LOCK, M32R2F_SFMT_MACHI_A, M32R2F_SFMT_MULHI_A, M32R2F_SFMT_= MV=0A= , M32R2F_SFMT_MVFACHI_A, M32R2F_SFMT_MVFC, M32R2F_SFMT_MVTACHI_A, M32R2F_S= FMT_MVTC=0A= , M32R2F_SFMT_NOP, M32R2F_SFMT_RAC_DSI, M32R2F_SFMT_RTE, M32R2F_SFMT_SETH= =0A= , M32R2F_SFMT_SLL3, M32R2F_SFMT_SLLI, M32R2F_SFMT_ST, M32R2F_SFMT_ST_D=0A= , M32R2F_SFMT_STB, M32R2F_SFMT_STB_D, M32R2F_SFMT_STH, M32R2F_SFMT_STH_D= =0A= , M32R2F_SFMT_ST_PLUS, M32R2F_SFMT_STH_PLUS, M32R2F_SFMT_STB_PLUS, M32R2F_= SFMT_TRAP=0A= , M32R2F_SFMT_UNLOCK, M32R2F_SFMT_SATB, M32R2F_SFMT_SAT, M32R2F_SFMT_SADD= =0A= , M32R2F_SFMT_MACWU1, M32R2F_SFMT_MSBLO, M32R2F_SFMT_MULWU1, M32R2F_SFMT_S= C=0A= , M32R2F_SFMT_CLRPSW, M32R2F_SFMT_SETPSW, M32R2F_SFMT_BSET, M32R2F_SFMT_BT= ST=0A= } M32R2F_SFMT_TYPE;=0A= =0A= /* Function unit handlers (user written). */=0A= =0A= extern int m32r2f_model_m32r2_u_store (SIM_CPU *, const IDESC *, int /*unit= _num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);=0A= extern int m32r2f_model_m32r2_u_load (SIM_CPU *, const IDESC *, int /*unit_= num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);=0A= extern int m32r2f_model_m32r2_u_cti (SIM_CPU *, const IDESC *, int /*unit_n= um*/, int /*referenced*/, INT /*sr*/);=0A= extern int m32r2f_model_m32r2_u_mac (SIM_CPU *, const IDESC *, int /*unit_n= um*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);=0A= extern int m32r2f_model_m32r2_u_cmp (SIM_CPU *, const IDESC *, int /*unit_n= um*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);=0A= extern int m32r2f_model_m32r2_u_exec (SIM_CPU *, const IDESC *, int /*unit_= num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);=0A= =0A= /* Profiling before/after handlers (user written) */=0A= =0A= extern void m32r2f_model_insn_before (SIM_CPU *, int /*first_p*/);=0A= extern void m32r2f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycle= s*/);=0A= =0A= #endif /* M32R2F_DECODE_H */=0A= --Boundary_(ID_E6X7Qq+t7eFmEyw04Re/AQ)--