ChangeLog/sim/m32r

2003-12-02  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>

        * Makefile.in : Add new machine m32r2.
        * m32r2.c : New file for m32r2.
	* mloop2.in : Ditto
	* model2.c : Ditto
	* sem2-switch.c : Ditto
        * m32r-sim.h : Add EVB register.
        * sim-if.h : Ditto
        * sim-main.h : Ditto
        * traps.c : Ditto

Index: sim/m32r/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/m32r/Makefile.in,v
retrieving revision 1.6
diff -c -r1.6 Makefile.in
*** sim/m32r/Makefile.in	8 Sep 2003 17:26:20 -0000	1.6
--- sim/m32r/Makefile.in	2 Dec 2003 08:56:19 -0000
***************
*** 22,27 ****
--- 22,28 ----
  
  M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
  M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
+ M32R2_OBJS = m32r2.o cpu2.o decode2.o model2.o mloop2.o
  
  CONFIG_DEVICES = dv-sockser.o
  CONFIG_DEVICES =
***************
*** 38,43 ****
--- 39,45 ----
  	sim-if.o arch.o \
  	$(M32R_OBJS) \
  	$(M32RX_OBJS) \
+ 	$(M32R2_OBJS) \
  	traps.o devices.o \
  	$(CONFIG_DEVICES)
  
***************
*** 113,122 ****
  semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
  modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
  
  m32r-clean:
  	rm -f mloop.c eng.h stamp-mloop
  	rm -f mloopx.c engx.h stamp-xmloop
! 	rm -f stamp-arch stamp-cpu stamp-xcpu
  	rm -f tmp-*
  
  # cgen support, enable with --enable-cgen-maint
--- 115,149 ----
  semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
  modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
  
+ # M32R2 objs
+                                                                                 
+ M32R2F_INCLUDE_DEPS = \
+ 	$(CGEN_MAIN_CPU_DEPS) \
+ 	cpu2.h decode2.h eng2.h
+                                                                                 
+ m32r2.o: m32r2.c $(M32R2F_INCLUDE_DEPS)
+                                                                                 
+ # FIXME: Use of `mono' is wip.
+ mloop2.c eng2.h: stamp-2mloop
+ stamp-2mloop: $(srcdir)/../common/genmloop.sh mloop2.in Makefile
+ 	$(SHELL) $(srccom)/genmloop.sh \
+ 		-mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
+ 		-cpu m32r2f -infile $(srcdir)/mloop2.in
+ 	$(SHELL) $(srcroot)/move-if-change eng.hin eng2.h
+ 	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop2.c
+ 	touch stamp-2mloop
+ mloop2.o: mloop2.c sem2-switch.c $(M32R2F_INCLUDE_DEPS)
+ 
+ cpu2.o: cpu2.c $(M32R2F_INCLUDE_DEPS)
+ decode2.o: decode2.c $(M32R2F_INCLUDE_DEPS)
+ sem2.o: sem2.c $(M32R2F_INCLUDE_DEPS)
+ model2.o: model2.c $(M32R2F_INCLUDE_DEPS)
+ 
  m32r-clean:
  	rm -f mloop.c eng.h stamp-mloop
  	rm -f mloopx.c engx.h stamp-xmloop
! 	rm -f mloop2.c eng2.h stamp-2mloop
! 	rm -f stamp-arch stamp-cpu stamp-xcpu stamp-2cpu
  	rm -f tmp-*
  
  # cgen support, enable with --enable-cgen-maint
***************
*** 148,150 ****
--- 175,187 ----
  	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
  	touch stamp-xcpu
  cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
+ 
+ stamp-2cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/m32r.cpu
+ 	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ 	  cpu=m32r2f mach=m32r2 SUFFIX=2 \
+ 	  archfile=$(CGEN_CPU_DIR)/m32r.cpu \
+ 	  FLAGS="with-scache with-profile=fn" \
+ 	  EXTRAFILES="$(CGEN_CPU_SEMSW)"
+ 	touch stamp-2cpu
+ cpu2.h sem2-switch.c model2.c decode2.c decode2.h: $(CGEN_MAINT) stamp-2cpu
+ 
Index: sim/m32r/m32r-sim.h
===================================================================
RCS file: /cvs/src/src/sim/m32r/m32r-sim.h,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 m32r-sim.h
*** sim/m32r/m32r-sim.h	12 Oct 1999 04:37:53 -0000	1.1.1.3
--- sim/m32r/m32r-sim.h	2 Dec 2003 08:56:20 -0000
***************
*** 34,39 ****
--- 34,40 ----
  #define ACC1H_REGNUM	25
  #define BBPSW_REGNUM	26
  #define BBPC_REGNUM	27
+ #define EVB_REGNUM	28
  
  extern int m32r_decode_gdb_ctrl_regnum (int);
  
Index: sim/m32r/m32r.c
===================================================================
RCS file: /cvs/src/src/sim/m32r/m32r.c,v
retrieving revision 1.1.1.2
diff -c -r1.1.1.2 m32r.c
*** sim/m32r/m32r.c	26 Apr 1999 18:32:56 -0000	1.1.1.2
--- sim/m32r/m32r.c	2 Dec 2003 08:56:20 -0000
***************
*** 39,44 ****
--- 39,45 ----
        case BPC_REGNUM : return H_CR_BPC;
        case BBPSW_REGNUM : return H_CR_BBPSW;
        case BBPC_REGNUM : return H_CR_BBPC;
+       case EVB_REGNUM : return H_CR_CR5;
      }
    abort ();
  }
***************
*** 62,87 ****
        case BPC_REGNUM :
        case BBPSW_REGNUM :
        case BBPC_REGNUM :
  	SETTWI (buf, a_m32r_h_cr_get (current_cpu,
  				      m32r_decode_gdb_ctrl_regnum (rn)));
  	break;
        case PC_REGNUM :
  	if (mach == MACH_M32R)
  	  SETTWI (buf, m32rbf_h_pc_get (current_cpu));
! 	else
  	  SETTWI (buf, m32rxf_h_pc_get (current_cpu));
  	break;
        case ACCL_REGNUM :
  	if (mach == MACH_M32R)
  	  SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
! 	else
  	  SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
  	break;
        case ACCH_REGNUM :
  	if (mach == MACH_M32R)
  	  SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
! 	else
  	  SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
  	break;
        default :
  	return 0;
--- 63,95 ----
        case BPC_REGNUM :
        case BBPSW_REGNUM :
        case BBPC_REGNUM :
+       case EVB_REGNUM :
  	SETTWI (buf, a_m32r_h_cr_get (current_cpu,
  				      m32r_decode_gdb_ctrl_regnum (rn)));
  	break;
        case PC_REGNUM :
  	if (mach == MACH_M32R)
  	  SETTWI (buf, m32rbf_h_pc_get (current_cpu));
! 	else if (mach == MACH_M32RX)
  	  SETTWI (buf, m32rxf_h_pc_get (current_cpu));
+ 	else
+ 	  SETTWI (buf, m32r2f_h_pc_get (current_cpu));
  	break;
        case ACCL_REGNUM :
  	if (mach == MACH_M32R)
  	  SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
! 	else if (mach == MACH_M32RX)
  	  SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
+ 	else
+ 	  SETTWI (buf, GETLODI (m32r2f_h_accum_get (current_cpu)));
  	break;
        case ACCH_REGNUM :
  	if (mach == MACH_M32R)
  	  SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
! 	else if (mach == MACH_M32RX)
  	  SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
+ 	else
+ 	  SETTWI (buf, GETHIDI (m32r2f_h_accum_get (current_cpu)));
  	break;
        default :
  	return 0;
***************
*** 109,114 ****
--- 117,123 ----
        case BPC_REGNUM :
        case BBPSW_REGNUM :
        case BBPC_REGNUM :
+       case EVB_REGNUM :
  	a_m32r_h_cr_set (current_cpu,
  			 m32r_decode_gdb_ctrl_regnum (rn),
  			 GETTWI (buf));
***************
*** 116,136 ****
        case PC_REGNUM :
  	if (mach == MACH_M32R)
  	  m32rbf_h_pc_set (current_cpu, GETTWI (buf));
! 	else
  	  m32rxf_h_pc_set (current_cpu, GETTWI (buf));
  	break;
        case ACCL_REGNUM :
  	{
  	  DI val;
  	  if (mach == MACH_M32R)
  	    val = m32rbf_h_accum_get (current_cpu);
! 	  else
  	    val = m32rxf_h_accum_get (current_cpu);
  	  SETLODI (val, GETTWI (buf));
  	  if (mach == MACH_M32R)
  	    m32rbf_h_accum_set (current_cpu, val);
! 	  else
  	    m32rxf_h_accum_set (current_cpu, val);
  	  break;
  	}
        case ACCH_REGNUM :
--- 125,151 ----
        case PC_REGNUM :
  	if (mach == MACH_M32R)
  	  m32rbf_h_pc_set (current_cpu, GETTWI (buf));
! 	else if (mach == MACH_M32RX)
  	  m32rxf_h_pc_set (current_cpu, GETTWI (buf));
+ 	else
+ 	  m32r2f_h_pc_set (current_cpu, GETTWI (buf));
  	break;
        case ACCL_REGNUM :
  	{
  	  DI val;
  	  if (mach == MACH_M32R)
  	    val = m32rbf_h_accum_get (current_cpu);
! 	  else if (mach == MACH_M32RX)
  	    val = m32rxf_h_accum_get (current_cpu);
+ 	  else
+ 	    val = m32r2f_h_accum_get (current_cpu);
  	  SETLODI (val, GETTWI (buf));
  	  if (mach == MACH_M32R)
  	    m32rbf_h_accum_set (current_cpu, val);
! 	  else if (mach == MACH_M32RX)
  	    m32rxf_h_accum_set (current_cpu, val);
+ 	  else
+ 	    m32r2f_h_accum_set (current_cpu, val);
  	  break;
  	}
        case ACCH_REGNUM :
***************
*** 138,150 ****
  	  DI val;
  	  if (mach == MACH_M32R)
  	    val = m32rbf_h_accum_get (current_cpu);
! 	  else
  	    val = m32rxf_h_accum_get (current_cpu);
  	  SETHIDI (val, GETTWI (buf));
  	  if (mach == MACH_M32R)
  	    m32rbf_h_accum_set (current_cpu, val);
! 	  else
  	    m32rxf_h_accum_set (current_cpu, val);
  	  break;
  	}
        default :
--- 153,169 ----
  	  DI val;
  	  if (mach == MACH_M32R)
  	    val = m32rbf_h_accum_get (current_cpu);
! 	  else if (mach == MACH_M32RX)
  	    val = m32rxf_h_accum_get (current_cpu);
+ 	  else
+ 	    val = m32r2f_h_accum_get (current_cpu);
  	  SETHIDI (val, GETTWI (buf));
  	  if (mach == MACH_M32R)
  	    m32rbf_h_accum_set (current_cpu, val);
! 	  else if (mach == MACH_M32RX)
  	    m32rxf_h_accum_set (current_cpu, val);
+ 	  else
+ 	    m32r2f_h_accum_set (current_cpu, val);
  	  break;
  	}
        default :
***************
*** 169,174 ****
--- 188,197 ----
      case MACH_M32RX : 
        return m32rxf_h_gr_get (current_cpu, regno);
  #endif
+ #ifdef HAVE_CPU_M32R2F
+     case MACH_M32R2 : 
+       return m32r2f_h_gr_get (current_cpu, regno);
+ #endif
      default :
        abort ();
      }
***************
*** 189,194 ****
--- 212,222 ----
        m32rxf_h_gr_set (current_cpu, regno, newval);
        break;
  #endif
+ #ifdef HAVE_CPU_M32RXF
+     case MACH_M32R2 : 
+       m32r2f_h_gr_set (current_cpu, regno, newval);
+       break;
+ #endif
      default :
        abort ();
      }
***************
*** 207,212 ****
--- 235,244 ----
      case MACH_M32RX : 
        return m32rxf_h_cr_get (current_cpu, regno);
  #endif
+ #ifdef HAVE_CPU_M32R2F
+     case MACH_M32R2 : 
+       return m32r2f_h_cr_get (current_cpu, regno);
+ #endif
      default :
        abort ();
      }
***************
*** 225,230 ****
--- 257,267 ----
  #ifdef HAVE_CPU_M32RXF
      case MACH_M32RX : 
        m32rxf_h_cr_set (current_cpu, regno, newval);
+       break;
+ #endif
+ #ifdef HAVE_CPU_M32RXF
+     case MACH_M32R2 : 
+       m32r2f_h_cr_set (current_cpu, regno, newval);
        break;
  #endif
      default :
Index: sim/m32r/sim-if.c
===================================================================
RCS file: /cvs/src/src/sim/m32r/sim-if.c,v
retrieving revision 1.2
diff -c -r1.2 sim-if.c
*** sim/m32r/sim-if.c	27 Feb 2003 23:26:34 -0000	1.2
--- sim/m32r/sim-if.c	2 Dec 2003 08:56:23 -0000
***************
*** 240,245 ****
--- 240,250 ----
  		       PROFILE_LABEL_WIDTH, "Parallel insns:",
  		       sim_add_commas (buf, sizeof (buf),
  				       CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
+       if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
+ 	sim_io_printf (sd, "  %-*s %s\n\n",
+ 		       PROFILE_LABEL_WIDTH, "Parallel insns:",
+ 		       sim_add_commas (buf, sizeof (buf),
+ 				       CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
      }
  }
  
Index: sim/m32r/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/m32r/sim-main.h,v
retrieving revision 1.1.1.2
diff -c -r1.1.1.2 sim-main.h
*** sim/m32r/sim-main.h	12 Oct 1999 04:37:53 -0000	1.1.1.2
--- sim/m32r/sim-main.h	2 Dec 2003 08:56:23 -0000
***************
*** 60,65 ****
--- 60,67 ----
    M32RBF_CPU_DATA cpu_data;
  #elif defined (WANT_CPU_M32RXF)
    M32RXF_CPU_DATA cpu_data;
+ #elif defined (WANT_CPU_M32R2F)
+   M32R2F_CPU_DATA cpu_data;
  #endif
  };
  
Index: sim/m32r/traps.c
===================================================================
RCS file: /cvs/src/src/sim/m32r/traps.c,v
retrieving revision 1.1.1.3
diff -c -r1.1.1.3 traps.c
*** sim/m32r/traps.c	5 Oct 1999 23:13:56 -0000	1.1.1.3
--- sim/m32r/traps.c	2 Dec 2003 08:56:23 -0000
***************
*** 21,26 ****
--- 21,27 ----
  #include "sim-main.h"
  #include "targ-vals.h"
  
+ #define TRAP_FLUSH_CACHE 12
  /* The semantic code invokes this for invalid (unrecognized) instructions.
     CIA is the address with the invalid insn.
     VPC is the virtual pc of the following insn.  */
***************
*** 68,79 ****
  	  /* sm not changed */
  	  m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
  	}
!       else
  	{
  	  m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
  	  /* sm not changed */
  	  m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
  	}
        a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
  
        sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
--- 69,86 ----
  	  /* sm not changed */
  	  m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
  	}
!       else if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32RX)
  	{
  	  m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
  	  /* sm not changed */
  	  m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
  	}
+       else
+ 	{
+ 	  m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
+ 	  /* sm not changed */
+ 	  m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
+ 	}
        a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
  
        sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
***************
*** 131,138 ****
    if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
      {
        /* The new pc is the trap vector entry.
! 	 We assume there's a branch there to some handler.  */
!       USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
        return new_pc;
      }
  
--- 138,147 ----
    if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
      {
        /* The new pc is the trap vector entry.
! 	 We assume there's a branch there to some handler.
!          Use cr5 as EVB (EIT Vector Base) register.  */
!       /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
!       USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
        return new_pc;
      }
  
***************
*** 169,177 ****
  		       sim_stopped, SIM_SIGTRAP);
        break;
  
      default :
        {
! 	USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
  	return new_pc;
        }
      }
--- 178,192 ----
  		       sim_stopped, SIM_SIGTRAP);
        break;
  
+     case TRAP_FLUSH_CACHE:
+       /* Do nothing.  */
+       break;
+ 
      default :
        {
! 	/* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
!         /* Use cr5 as EVB (EIT Vector Base) register.  */
!         USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
  	return new_pc;
        }
      }
