diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/allinsn.d ./allinsn.d
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/allinsn.d	Mon May  3 16:28:51 1999
--- ./allinsn.d	Fri Dec 19 10:23:47 2003
***************
*** 209,215 ****
  
  0+010c <ld24>:
   10c:	ed 00 00 00 	ld24 fp,[#]*0 <add>
! 			10c: R_M32R_24	.data
  
  0+0110 <ldi8>:
   110:	6d 00 f0 00 	ldi fp,[#]*0 \|\| nop
--- 209,215 ----
  
  0+010c <ld24>:
   10c:	ed 00 00 00 	ld24 fp,[#]*0 <add>
! 			10c: R_M32R_24_RELA	.data
  
  0+0110 <ldi8>:
   110:	6d 00 f0 00 	ldi fp,[#]*0 \|\| nop
diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/high-1.d ./high-1.d
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/high-1.d	Mon May  3 16:28:51 1999
--- ./high-1.d	Fri Dec 19 12:37:29 2003
***************
*** 7,16 ****
  Disassembly of section .text:
  
  0* <foo>:
!  *0:	d4 c0 00 01 	seth r4,[#]*0x1
! [ 	]*0: R_M32R_HI16_ULO	.text
   *4:	84 e4 00 00 	or3 r4,r4,[#]*0x0
! [ 	]*4: R_M32R_LO16	.text
   *8:	d4 c0 12 34 	seth r4,[#]*0x1234
   *c:	84 e4 87 65 	or3 r4,r4,[#]*0x8765
   *10:	d4 c0 12 35 	seth r4,[#]*0x1235
--- 7,16 ----
  Disassembly of section .text:
  
  0* <foo>:
!  *0:	d4 c0 00 00 	seth r4,[#]*0x0
! [ 	]*0: R_M32R_HI16_ULO_RELA	.text\+0x10000
   *4:	84 e4 00 00 	or3 r4,r4,[#]*0x0
! [ 	]*4: R_M32R_LO16_RELA	.text\+0x10000
   *8:	d4 c0 12 34 	seth r4,[#]*0x1234
   *c:	84 e4 87 65 	or3 r4,r4,[#]*0x8765
   *10:	d4 c0 12 35 	seth r4,[#]*0x1235
diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/m32rx.d ./m32rx.d
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/m32rx.d	Tue Oct  5 10:27:35 1999
--- ./m32rx.d	Fri Dec 19 12:32:31 2003
***************
*** 85,112 ****
    64:	54 81 f0 00 	rach a1,a0,#0x2 \|\| nop
  
  0+0068 <bc__add>:
!   68:	7c e6 8d ad 	bc 0 <bcl> \|\| add fp,fp
!   6c:	7c e5 0d ad 	bc 0 <bcl> -> add fp,fp
  
  0+0070 <bcl__addi>:
!   70:	78 e4 cd 4d 	bcl 0 <bcl> \|\| addi fp,#77
!   74:	78 e3 cd 4d 	bcl 0 <bcl> \|\| addi fp,#77
  
  0+0078 <bl__addv>:
!   78:	7e e2 8d 8d 	bl 0 <bcl> \|\| addv fp,fp
!   7c:	7e e1 8d 8d 	bl 0 <bcl> \|\| addv fp,fp
  
  0+0080 <bnc__addx>:
!   80:	7d e0 8d 9d 	bnc 0 <bcl> \|\| addx fp,fp
!   84:	7d df 0d 9d 	bnc 0 <bcl> -> addx fp,fp
  
  0+0088 <bncl__and>:
!   88:	79 de 8d cd 	bncl 0 <bcl> \|\| and fp,fp
!   8c:	0d cd 79 dd 	and fp,fp -> bncl 0 <bcl>
  
  0+0090 <bra__cmp>:
!   90:	7f dc 8d 4d 	bra 0 <bcl> \|\| cmp fp,fp
!   94:	7f db 8d 4d 	bra 0 <bcl> \|\| cmp fp,fp
  
  0+0098 <jl__cmpeq>:
    98:	1e cd 8d 6d 	jl fp \|\| cmpeq fp,fp
--- 85,124 ----
    64:	54 81 f0 00 	rach a1,a0,#0x2 \|\| nop
  
  0+0068 <bc__add>:
!   68:	7c 00 8d ad 	bc 68 <bc__add> \|\| add fp,fp
! 			68: R_M32R_10_PCREL_RELA	bcl
!   6c:	7c 00 0d ad 	bc 6c <bc__add\+0x4> -> add fp,fp
! 			6c: R_M32R_10_PCREL_RELA	bcl
  
  0+0070 <bcl__addi>:
!   70:	78 00 cd 4d 	bcl 70 <bcl__addi> \|\| addi fp,#77
! 			70: R_M32R_10_PCREL_RELA	bcl
!   74:	78 00 cd 4d 	bcl 74 <bcl__addi\+0x4> \|\| addi fp,#77
! 			74: R_M32R_10_PCREL_RELA	bcl
  
  0+0078 <bl__addv>:
!   78:	7e 00 8d 8d 	bl 78 <bl__addv> \|\| addv fp,fp
! 			78: R_M32R_10_PCREL_RELA	bcl
!   7c:	7e 00 8d 8d 	bl 7c <bl__addv\+0x4> \|\| addv fp,fp
! 			7c: R_M32R_10_PCREL_RELA	bcl
  
  0+0080 <bnc__addx>:
!   80:	7d 00 8d 9d 	bnc 80 <bnc__addx> \|\| addx fp,fp
! 			80: R_M32R_10_PCREL_RELA	bcl
!   84:	7d 00 0d 9d 	bnc 84 <bnc__addx\+0x4> -> addx fp,fp
! 			84: R_M32R_10_PCREL_RELA	bcl
  
  0+0088 <bncl__and>:
!   88:	79 00 8d cd 	bncl 88 <bncl__and> \|\| and fp,fp
! 			88: R_M32R_10_PCREL_RELA	bcl
!   8c:	79 00 8d cd 	bncl 8c <bncl__and\+0x4> \|\| and fp,fp
! 			8c: R_M32R_10_PCREL_RELA	bcl
  
  0+0090 <bra__cmp>:
!   90:	7f 00 8d 4d 	bra 90 <bra__cmp> \|\| cmp fp,fp
! 			90: R_M32R_10_PCREL_RELA	bcl
!   94:	7f 00 8d 4d 	bra 94 <bra__cmp\+0x4> \|\| cmp fp,fp
! 			94: R_M32R_10_PCREL_RELA	bcl
  
  0+0098 <jl__cmpeq>:
    98:	1e cd 8d 6d 	jl fp \|\| cmpeq fp,fp
diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/m32rx.s ./m32rx.s
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/m32rx.s	Tue Oct  5 10:27:35 1999
--- ./m32rx.s	Fri Dec 19 12:25:20 2003
***************
*** 172,178 ****
  bncl__and:
  	bncl bcl || and fp, fp
  	and fp, fp
! 	bncl bcl
  
  	.text
  	.global bra__cmp
--- 172,178 ----
  bncl__and:
  	bncl bcl || and fp, fp
  	and fp, fp
! 	bncl.s bcl
  
  	.text
  	.global bra__cmp
diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/pic.d ./pic.d
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/pic.d	Thu Jan  1 09:00:00 1970
--- ./pic.d	Fri Dec 19 13:34:29 2003
***************
*** 0 ****
--- 1,47 ----
+ #as: -K PIC
+ #objdump: -dr 
+ #name: pic
+ 
+ .*: +file format .*
+ 
+ Disassembly of section .text:
+ 
+ 0+0000 <pic_gotpc>:
+    0:	7e 01 f0 00 	bl 4 <pic_gotpc\+0x4> \|\| nop
+    4:	ec 00 00 00 	ld24 r12,0 <pic_gotpc>
+ 			4: R_M32R_GOTPC24	_GLOBAL_OFFSET_TABLE_
+    8:	0c ae f0 00 	add r12,lr \|\| nop
+ 
+ 0+000c <pic_gotpc_slo>:
+    c:	7e 01 f0 00 	bl 10 <pic_gotpc_slo\+0x4> \|\| nop
+   10:	dc c0 00 00 	seth r12,[#]0x0
+ 			10: R_M32R_GOTPC_HI_SLO	_GLOBAL_OFFSET_TABLE_
+   14:	8c ac 00 00 	add3 r12,r12,[#]0
+ 			14: R_M32R_GOTPC_LO	_GLOBAL_OFFSET_TABLE_\+0x4
+   18:	0c ae f0 00 	add r12,lr \|\| nop
+ 
+ 0+001c <pic_gotpc_ulo>:
+   1c:	7e 01 f0 00 	bl 20 <pic_gotpc_ulo\+0x4> \|\| nop
+   20:	dc c0 00 00 	seth r12,[#]0x0
+ 			20: R_M32R_GOTPC_HI_ULO	_GLOBAL_OFFSET_TABLE_
+   24:	8c ec 00 00 	or3 r12,r12,[#]0x0
+ 			24: R_M32R_GOTPC_LO	_GLOBAL_OFFSET_TABLE_\+0x4
+   28:	0c ae f0 00 	add r12,lr \|\| nop
+ 
+ 0+002c <pic_got>:
+   2c:	e0 00 00 00 	ld24 r0,0 <pic_gotpc>
+ 			2c: R_M32R_GOT24	sym
+ 
+ 0+0030 <pic_got16>:
+   30:	dc c0 00 00 	seth r12,[#]0x0
+ 			30: R_M32R_GOT16_HI_SLO	sym2
+   34:	8c ac 00 00 	add3 r12,r12,[#]0
+ 			34: R_M32R_GOT16_LO	sym2\+0x4
+   38:	dc c0 00 00 	seth r12,[#]0x0
+ 			38: R_M32R_GOT16_HI_ULO	sym2
+   3c:	8c ec 00 00 	or3 r12,r12,[#]0x0
+ 			3c: R_M32R_GOT16_LO	sym2\+0x4
+ 
+ 0+0040 <pic_plt>:
+   40:	fe 00 00 00 	bl 40 <pic_plt>
+ 			40: R_M32R_26_PLTREL	func
diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/pic.exp ./pic.exp
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/pic.exp	Thu Jan  1 09:00:00 1970
--- ./pic.exp	Fri Dec 19 13:34:17 2003
***************
*** 0 ****
--- 1,5 ----
+ # M32R PIC testcases
+ 
+ if [istarget m32r*-*-*] {
+     run_dump_test "pic"
+ }
diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/pic.s ./pic.s
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/pic.s	Thu Jan  1 09:00:00 1970
--- ./pic.s	Fri Dec 19 12:57:58 2003
***************
*** 0 ****
--- 1,43 ----
+ 	.section .text
+ # R_M32R_GOTPC24
+ pic_gotpc:
+ 	bl.s .+4
+         ld24 r12,#_GLOBAL_OFFSET_TABLE_
+ 	add r12,lr
+ 
+ # R_M32R_GOTPC_HI_ULO
+ # R_M32R_GOTPC_HI_SLO
+ # R_M32R_GOTPC_LO
+ pic_gotpc_slo:
+ 	bl.s .+4
+         seth r12,#shigh(_GLOBAL_OFFSET_TABLE_)
+         add3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
+ 	add r12,lr
+ 
+ pic_gotpc_ulo:
+ 	bl.s .+4
+         seth r12,#high(_GLOBAL_OFFSET_TABLE_)
+         or3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
+ 	add r12,lr
+ 
+ # R_M32R_GOT24
+ pic_got:
+ 	.global sym
+ 	ld24 r0,#sym
+ 
+ # R_M32R_GOT16_HI_ULO
+ # R_M32R_GOT16_HI_SLO
+ # R_M32R_GOT16_LO
+ pic_got16:
+ 	.global sym2
+         seth r12,#shigh(sym2)
+         add3 r12,r12,#low(sym2+4)
+         seth r12,#high(sym2)
+         or3 r12,r12,#low(sym2+4)
+ 
+ # R_M32R_26_PLTREL
+ pic_plt:
+ 	.global func
+ 	bl func
+ 
+ 	.end
diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/relax-1.d ./relax-1.d
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/relax-1.d	Mon May  3 16:28:51 1999
--- ./relax-1.d	Fri Dec 19 10:26:25 2003
***************
*** 15,18 ****
  
  0* <branch>:
   *0:	ff 00 00 01 	bra 4 <Work>
! [ 	]*0: R_M32R_26_PCREL	.text
--- 15,18 ----
  
  0* <branch>:
   *0:	ff 00 00 01 	bra 4 <Work>
! [ 	]*0: R_M32R_26_PCREL_RELA	.text
diff -crN ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/uppercase.d ./uppercase.d
*** ../../../../../../org/binutils/src/gas/testsuite/gas/m32r/uppercase.d	Mon May  3 16:28:51 1999
--- ./uppercase.d	Fri Dec 19 12:38:20 2003
***************
*** 11,26 ****
  
  0+0004 <high>:
     4:	d0 c0 00 00 	seth r0,#0x0
! [ 	]*4: R_M32R_HI16_ULO	[.]text
  
  0+0008 <shigh>:
     8:	d0 c0 00 00 	seth r0,#0x0
! [ 	]*8: R_M32R_HI16_SLO	[.]text
  
  0+000c <low>:
!    c:	80 e0 00 0c 	or3 r0,r0,#0xc
! [ 	]*c: R_M32R_LO16	[.]text
  
  0+0010 <sda>:
    10:	80 a0 00 00 	add3 r0,r0,#0
! [ 	]*10: R_M32R_SDA16	sdavar
--- 11,26 ----
  
  0+0004 <high>:
     4:	d0 c0 00 00 	seth r0,#0x0
! [ 	]*4: R_M32R_HI16_ULO_RELA	[.]text\+0x4
  
  0+0008 <shigh>:
     8:	d0 c0 00 00 	seth r0,#0x0
! [ 	]*8: R_M32R_HI16_SLO_RELA	[.]text\+0x8
  
  0+000c <low>:
!    c:	80 e0 00 00 	or3 r0,r0,#0x0
! [ 	]*c: R_M32R_LO16_RELA	[.]text\+0xc
  
  0+0010 <sda>:
    10:	80 a0 00 00 	add3 r0,r0,#0
! [ 	]*10: R_M32R_SDA16_RELA	sdavar
