From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gdb-patches-return-36492-listarch-gdb-patches=sources.redhat.com@sources.redhat.com>
Received: (qmail 5836 invoked by alias); 26 Oct 2004 05:45:20 -0000
Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm
Precedence: bulk
List-Subscribe: <mailto:gdb-patches-subscribe@sources.redhat.com>
List-Archive: <http://sources.redhat.com/ml/gdb-patches/>
List-Post: <mailto:gdb-patches@sources.redhat.com>
List-Help: <mailto:gdb-patches-help@sources.redhat.com>, <http://sources.redhat.com/ml/#faqs>
Sender: gdb-patches-owner@sources.redhat.com
Received: (qmail 5822 invoked from network); 26 Oct 2004 05:45:19 -0000
Received: from unknown (HELO mail01.idc.renesas.com) (202.234.163.13)
  by sourceware.org with SMTP; 26 Oct 2004 05:45:19 -0000
Received: (from root@localhost)
	by guardian05.idc.renesas.com with  id i9Q5j9W7028698;
	Tue, 26 Oct 2004 14:45:09 +0900 (JST)
Received: from unknown [172.20.8.69] by guardian05.idc.renesas.com with SMTP id QAA28697 ; Tue, 26 Oct 2004 14:45:08 +0900
Received: from mrkaisv.hoku.renesas.com ([10.145.105.245])
	by rnsmtp01.hoku_r.renesas.com (8.9.3/3.7W) with ESMTP id OAA03976;
	Tue, 26 Oct 2004 14:45:06 +0900 (JST)
Received: from E5A02646 (unknown [10.145.105.81])
	by mrkaisv.hoku.renesas.com (Postfix) with SMTP
	id 8E31E7981B7; Tue, 26 Oct 2004 14:45:04 +0900 (JST)
Message-ID: <002001c4bb1f$20031630$5169910a@E5A02646>
From: "Kei Sakamoto" <sakamoto.kei@renesas.com>
To: "Daniel Jacobowitz" <drow@false.org>
Cc: <gdb-patches@sources.redhat.com>
References: <01b101c4ac37$3adbf950$5169910a@E5A02646> <20041025153816.GA28488@nevyn.them.org>
Subject: Re: [RFA/m32r] Fix breakpoint bug
Date: Tue, 26 Oct 2004 05:45:00 -0000
MIME-Version: 1.0
Content-Type: text/plain;
	charset="ISO-8859-1"
Content-Transfer-Encoding: 7bit
X-SW-Source: 2004-10/txt/msg00431.txt.bz2

> I'm curious about the little endian case:
> 
> +  else /* little-endian */
> +    {
> +      if ((addr & 3) == 0)
> + {
> +   buf[0] = contents_cache[0];
> +   buf[1] = contents_cache[1] & 0x7f;
> +   buf[2] = bp_entry[1];
> +   buf[3] = bp_entry[0];
>   }
> 
> Shouldn't the breakpoint be placed at buf[0] here rather than buf[2]?

For most of architectures - yes, it shold be at buf[0]. But the little endian
mode of M32R is a kind of unique.

In other architectures, two 16-bit instructions, A and B, are placed as
the following:

Big endian:
A0 A1 B0 B1

Little endian:
A1 A0  B1 B0

In M32R, they are placed like this:

Big endian:
A0 A1 B0 B1

Little endian:
B1 B0 A1 A0

This is because M32R always fetches instructions in 32-bit.
So the breakpoint should be placed at buf[2].

Kei Sakamoto