From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 84770 invoked by alias); 9 Oct 2017 16:55:54 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 84750 invoked by uid 89); 9 Oct 2017 16:55:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy=choices, cpuc, month X-HELO: mail-pf0-f201.google.com Received: from mail-pf0-f201.google.com (HELO mail-pf0-f201.google.com) (209.85.192.201) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Oct 2017 16:55:51 +0000 Received: by mail-pf0-f201.google.com with SMTP id u70so4998261pfa.2 for ; Mon, 09 Oct 2017 09:55:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:message-id:date:subject:from:to:cc; bh=Bhth7DKopmaoq4lWais4b1VTJkUbFcbcXLqV5LnJMhI=; b=T6QOjoPeNCCvMuaGj0oVENFuDvfj1cIIAmlh0eNc/J/pJlgYBQ6PDLRyuVQ9BrAeGq Bk7bmDwvqgIpA93QEVqhdq9KhrwdkOaEnNSLb1CynSnytvp+6FBuCBLegLXpuF1P9NiX 5Tv5v5otd5EZ0uSIIEj4/7K/pVKYCW7k3z/Z2cmDeM/NZYnqmWdtYsdjO5YaWedxHU9X hS/oRPC4Z0tKeA9nJl41hwQVuy/YCdnfL7NrX5Px23fvHcOayLplzlerZObuF0v6S8b3 Hw2IPYwAyHds15k4qAH5UgTGXQ/0xTf/rbakQOPhI54NwatFiSQXoObAZSe4PuYM2h2R U+2w== X-Gm-Message-State: AMCzsaUdE7l8dmG/FX0azqLg2SjM0bjHQXqbO+dU8smmEUfSr39nk0Ty ok/1Ycvhqj4URxb6995kdtHj2l8= X-Google-Smtp-Source: AOwi7QCvpMS684n8RHRLKU857sw3aanCNr+7iA5hs+w00t3GLn60Lmym2auf57MvSXvHToz6hp5nq6A= MIME-Version: 1.0 X-Received: by 10.55.3.7 with SMTP id 7mr10253919qkd.29.1507568150397; Mon, 09 Oct 2017 09:55:50 -0700 (PDT) Message-ID: <001a114c9b6e14b276055b20101a@google.com> Date: Mon, 09 Oct 2017 16:55:00 -0000 Subject: Re: [PATCH v5 0/6] sim port for OpenRISC From: "Doug Evans via gdb-patches" Reply-To: Doug Evans To: Stafford Horne Cc: GDB patches , Openrisc , Mike Frysinger , Simon Marchi Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-10/txt/msg00222.txt.bz2 Stafford Horne writes: > Hello, > > (what I thought would be a few days turned into a month since the comments > on v4) > > Please find attached the sim patches that allow to get a basic OpenRISC > system running. This was used to verify the OpenRISC gdb port. > > The main author is Peter Gavin who should have his FSF copyright in place. > > Request for comments on: > - The testcase has a few tests commented out. I do not plan to fix now, > but hopefully be addressed after upstreaming. > > # Guide to Code # > > As Simon has requested I have tried to comment on the functions in the > simulator implementation. But I want to provide some general architecture > comments here for reference. Please let me know if there is a better place > for these kind of docs. fwiw, I'm totally ok with adding a README in a suitable directory. sim/or1k/README? I'm not too picky with what to put in there. You could add all of this and that would be fine by me. > The or1k sim uses the CGEN system to generate most of the simulator code. > There is some documentation for CGEN on sourceware.org here: > > https://sourceware.org/cgen/docs/cgen.html > > In the binutils-gdb project there are several files which get combined to > make up the CGEN simulator. The process for how those are built can be > seen in `or1k/Makefile.in`. But the main files are: > > MAIN > sim/common/nrun.c - the main() calls sim_open(), sim_resume() and others > sim/or1k/sim-if.c - implements sim_open() and others used by nrun > when envoking sim in gdb, gdb uses sim_open() directly > > CGEN input and generated files > cpu/or1k*.cpu - these define the hardware, model and semantics > sim/or1k/arch.c - generated defines sim_machs array > sim/or1k/cpu.c - *generated defines register setters and getters > sim/or1k/decode.c - generated defines instruction decoder > sim/or1k/model.c - generated defines instruction cycles > sim/or1k/sem.c - *generated defines instruction operation semantics > sim/or1k/sem-switch.c - *generated ditto but as a switch > > ENGINE runs decode execute loop > sim/common/cgen-* - cgen implementation helpers > sim/common/cgen-run.c - implements sim_resume() which runs the engine > sim/common/genmloop.sh - helper script to generate mloop.c engine the > decode, execute loop > sim/or1k/mloop.in - openRISC implementation of mloop parts > > EXTRAS callbacks from sem* to c code > sim/or1k/or1k.c - implements some instructions in c (not cgen schema) > sim/or1k/traps.c - exception handler > > For each sim architecture we have choices for how the mloop is implemented. > The OpenRISC engine uses scache pbb (pseudo-basic-block) instruction > extraction with both fast (sem-switch.c based) and full (sem.c based) > implementations. The fast and full modes are switch via the command line > options to the `run` command, i.e. --trace-insn will run in full mode. > > # Building # > > Simon asked for some details on how we build and test the openrisc sim. > Here are some details: > > ## TOOLCHAIN ## > > This may not be needed as binutils contains most/all of the utilities > required. But if needed, get this toolchain (this is the newlib binary, > others also available) > > https://github.com/openrisc/or1k-gcc/releases/download/or1k-5.4.0-20170218/or1k-elf-5.4.0-20170218.tar.xz > > If you want to build that from scratch look to: > > https://github.com/openrisc/newlib/blob/scripts/build.sh > > ## GDB ## > > In a directory along side binutils-gdb source > > mkdir build-or1k-elf-gdb > cd build-or1k-elf-gdb > > ../binutils-gdb/configure --target=or1k-elf \ > --prefix=/opt/shorne/software/or1k \ > --disable-itcl \ > --disable-tk \ > --disable-tcl \ > --disable-winsup \ > --disable-gdbtk \ > --disable-libgui \ > --disable-rda \ > --disable-sid \ > --with-sysroot \ > --disable-newlib \ > --disable-libgloss \ > --disable-gas \ > --disable-ld \ > --disable-binutils \ > --disable-gprof \ > --with-system-zlib > > # make gdb, sim > make > > # test sim > cd sim > make check > > The sim creates a binary simulator too, you can run binaries such as hello > world with: > > or1k-elf-gcc hello.c > ./or1k/run --trace-insn ./a.out > > # Test Results # > > Sim dejagnu tests were added specifically for openrisc and used to test > this. Please see the details of running the testsuite for sim below: > > === sim Summary === > > # of expected passes 18 > /home/shorne/work/openrisc/build-gdb/sim/or1k/run 0.5 > > > Thanks, > -Stafford