From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8800 invoked by alias); 9 Oct 2017 17:15:29 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 8737 invoked by uid 89); 9 Oct 2017 17:15:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-vk0-f74.google.com Received: from mail-vk0-f74.google.com (HELO mail-vk0-f74.google.com) (209.85.213.74) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Oct 2017 17:15:13 +0000 Received: by mail-vk0-f74.google.com with SMTP id b5so15416602vkf.3 for ; Mon, 09 Oct 2017 10:15:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:message-id:date:subject:from:to:cc; bh=MgXAPoThqZI23BG1EZeHUDpIMqi0EKDQv4kamGdtIRQ=; b=hSYJlkArz4nQLwPQ07CKytH8IIYpszypJbWWWX+5v5k7p9g4sDTnPhOgTwOTNasYZz rafmbdPMEkzdLPW+o22RxtZoXo7x5TrMDHFzBKygSitlRorzevEKo46Ke/obAFHefdqU CbxgycHurur5Oj4eeVAsYngnRKa2deIM2q0R+w1/eK6jPQxDSVTQckapq9dqLTLou7VE qCd9a2aVqrhrnkT3gzTS22jEJxboM6C7h2ymWGCvNd8vf9lQmuWqr7arFY+3NjVvyxNF d6UpiiOxhLozAldakO+/Ij6YObBeoB5Ppc5xeBlC8f9YreJIynYAZ75t3aAaPCnQfrXf s0/Q== X-Gm-Message-State: AMCzsaVkoDTdG9k/g/HKgQSgHbADHwd2OKaQf6bu70jUAmhPCx1xuX08 teVIrvMRxSR3EHKUOHMKaVqyjJM= X-Google-Smtp-Source: AOwi7QDstnMBua2OsbKXFqDBAQH3Yzcqpxl1kLigtA61L7Vs0140ritCTZmRnXeNPSvvmRB4VbneF8o= MIME-Version: 1.0 X-Received: by 10.55.78.70 with SMTP id c67mr9589700qkb.46.1507569308281; Mon, 09 Oct 2017 10:15:08 -0700 (PDT) Message-ID: <001a114a9bbe18b046055b2055bc@google.com> Date: Mon, 09 Oct 2017 17:15:00 -0000 Subject: Re: [PATCH v5 3/6] sim: or1k: add or1k target to sim From: "Doug Evans via gdb-patches" Reply-To: Doug Evans To: Simon Marchi Cc: Stafford Horne , GDB patches , Openrisc , Mike Frysinger Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2017-10/txt/msg00229.txt.bz2 Simon Marchi writes: > On 2017-10-05 09:49 AM, Stafford Horne wrote: > > This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN > > based sim so the bulk of the code is generated from the .cpu files by > > CGEN. The engine decode and execute logic in mloop uses scache with > > pseudo-basic-block extraction and supports both full and fast (switch) > > modes. > > > > The sim does not implement an mmu at the moment. The sim does implement > > fpu instructions via the common sim-fpu implementation. > > > > sim/ChangeLog: > > > > 2017-09-13 Stafford Horne > > Peter Gavin > > > > * configure.tgt: Add or1k sim. > > * or1k/Makefile.in: New file. > > * or1k/configure.ac: New file. > > * or1k/mloop.in: New file. > > * or1k/or1k-sim.h: New file. > > * or1k/or1k.c: New file. > > * or1k/sim-if.c: New file. > > * or1k/sim-main.h: New file. > > * or1k/traps.c: New file. > > ... > > > > +#define CHECK_SPR_FIELD(GROUP, INDEX, FIELD, test) \ > > + do { \ > > + USI field = GET_H_##SYS##_##INDEX##_##FIELD (); \ > > + if (!(test)) { \ > > + sim_io_eprintf(sd, "WARNING: unsupported %s field in %s register: 0x%x\n", \ > > 80 columns. fwiw, I don't mind the odd >80 column limit breaker. Moving the string to the next line may just work, but if it doesn't it's fine by me to just leave it.